Abstract: An antenna array decoupling method, apparatus and system, and a non-transitory computer-readable storage medium are disclosed. The method may include: receiving predetermined digital domain signals of a plurality of channels, each of the plurality of channels being a data channel corresponding to a respective one of array elements in an antenna array 5 (S110); determining decoupling factors of channels involved in decoupling corresponding to each channel, the decoupling factors being factors which have been solved for beforehand according to measured in-array pattern information of each array element in the antenna array (S120); and processing the predetermined digital domain signals of the channels involved in decoupling corresponding to each channel according to the decoupling factors to obtain a 10 decoupled predetermined digital domain signal of each channel (S130).

Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

Abstract: Methods, apparatus, and systems for reducing Peak Average Power Ratio (PAPR) in signal transmissions are described. In one example aspect, a wireless communication method includes determining, for an input sequence of coefficients, an output sequence and generating a waveform using the output sequence. The output sequence corresponds to an output of a convolutional modulation between a three-coefficient function associated with 2 2 , 1, and 2 2 and an intermediate sequence. The intermediate sequence is generated by inserting zero coefficients between coefficients of the input sequence of coefficients.

Abstract: Methods and apparatuses for codebook based UL transmission are provided. A method for operating a UE comprises transmitting a UE capability information about a UL codebook for 8 antenna ports; receiving an indication indicating a TPMI for a transmission of a PUSCH; and transmitting the PUSCH based on the indicated TPMI, wherein the TPMI indicates a precoding matrix from the UL codebook for the 8 antenna ports, the UL codebook includes full-coherent (FC) precoding matrices comprising all non-zero entries, and an l-th column of a FC precoding matrix is associated with an l-th layer of the PUSCH transmission.

Abstract: A transmitter and method therein for transmitting a signal to a receiver in a wireless communication system are disclosed. The transmitter is configured to modulate a signal using two different modulations, a combination of binary amplitude shift keying, ASK, and binary frequency shift keying, FSK, and transmit the modulated signal.

Abstract: A method for transmitting a signal, and an apparatus, a storage medium, and a user terminal are provided. The method includes: determining a plurality of baseband signals of Component Carriers (CC); selecting a plurality of phase rotation factors and recording a number of times of selection by adding one each time of selection; determining a candidate signal and a Peak to Average Power Ratio (PAPR) of the candidate signal, wherein in response to the PAPR being greater than or equal to a preset threshold and the number of times of selections not reaching a preset number of times, reselecting phase rotation factors and re-determining another candidate signal and a PAPR of the another candidate signal, until a PAPR is less than the preset threshold or the number of times of selections reaches the preset number of times; and transmitting the candidate signal.

Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: Embodiments of the present disclosure relate to system and method for generating a waveform in a communication network is disclosed. The method comprises determining precoder information using one of an indication from a base station and predetermined parameters corresponding to precoding. The predetermined parameters are one of coefficients of the precoding filter, and flatness requirement of the precoding filter. Also, the method comprises generating a sequence of output modulation symbols, wherein each output modulation symbol is obtained using a block of input data symbols and a lookup table. The lookup table is a function of the precoder information and predetermined modulation information. Next, the sequence of output modulation symbols is transformed using Discrete Fourier Transform to generate transformed output modulation symbols.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a converter configured to convert an analog signal into a digital signal based on a clock signal; a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal; a recovery circuit configured to recover the clock signal; and a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.

Abstract: Systems and methods are provided for reducing peak-to-average power ratio (“PAPR”) in an orthogonal frequency division multiplexing (“OFDM”) signal having reference tones by introducing modified pilot tones to cancel peaks in OFDM symbols in the OFDM signal array. The modified pilot tones are added to the original OFDM signal, which in turn conditions the OFDM symbols of the signal to effectively reduce the PAPR. Such systems and methods provide PAPR reduction for OFDM signals generated by an OFDM Signal Processor through the addition of tone reservation PAPR reduction methods, which use reserved tones such as pilot tones to improve PAPR. Such methods offer an advantage of improving the PAPR without introducing distortion to the signal.

Abstract: There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

Abstract: A method for detecting a constant envelope burst-mode radio frequency (RF) signal with a known periodic synchronization sequence (PSS) represented therein includes transforming an incoming RF signal into a digital baseband signal (DBS), and processing the phase domain part by: 1) applying a correlation algorithm to correlate the DBS with a synchronization pattern corresponding to the PSS, 2) filtering the resulting correlation signal for removing at least a DC component of the correlation signal, 3) down-sampling the filtered correlation signal with a sampling time controlled by a clock aligned with amplitude peaks in the filtered correlation signal, 4) performing a decision algorithm on the down-sampled signal to determine if PSS is present in the incoming RF signal, then 5) generating an output signal indicating if the known PSS is present in the incoming RF signal, in response to a result of the decision algorithm.

Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

Abstract: An apparatus includes a radio-frequency (RF) receiver for receiving RF signals. The RF receiver includes a plurality of modulation signal detectors (MSDs) to generate a plurality of detection signals when a plurality of RF signals modulated using a plurality of modulation schemes are detected. The RF receiver further includes a controller to cause reception of the plurality of RF signals in response to the plurality of detection signals.

Abstract: A method of joint encoding schemes with interleaver and tone mapper for multiple-resource unit (multi-RU) operation involves performing joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. The method also involves processing the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of resource units (RUs) on either or both of an aggregate-RU basis and an individual-RU basis to generate a plurality of processed bit sequences. The method further involves transmitting the plurality of processed bit sequences over the plurality of RUs.

Abstract: A characteristic variable antenna configured to be able to select or switch antenna characteristics in accordance with a predetermined periodic variable timing, an RF unit configured to perform a reception process on a signal received by the characteristic variable antenna, an ADC unit configured to sample the analog signal input from the RF unit at a sampling period corresponding to the variable timing of the antenna characteristics of the characteristic variable antenna, a signal dividing unit configured to divide the digital signal input from the ADC unit into different digital signals in accordance with the antenna characteristics and output the divided different digital signals, a MIMO-OFDM demodulation unit configured to receive inputs of the different digital signals divided by the signal dividing unit and perform a demodulation process of predetermined MIMO-OFDM, and a control unit configured to periodically select or switch the antenna characteristics of the characteristic variable antenna in accorda

Abstract: Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.

Abstract: A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value.

Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.