Abstract: A characteristic variable antenna configured to be able to select or switch antenna characteristics in accordance with a predetermined periodic variable timing, an RF unit configured to perform a reception process on a signal received by the characteristic variable antenna, an ADC unit configured to sample the analog signal input from the RF unit at a sampling period corresponding to the variable timing of the antenna characteristics of the characteristic variable antenna, a signal dividing unit configured to divide the digital signal input from the ADC unit into different digital signals in accordance with the antenna characteristics and output the divided different digital signals, a MIMO-OFDM demodulation unit configured to receive inputs of the different digital signals divided by the signal dividing unit and perform a demodulation process of predetermined MIMO-OFDM, and a control unit configured to periodically select or switch the antenna characteristics of the characteristic variable antenna in accorda

Abstract: Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.

Abstract: A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value.

Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Abstract: A method includes receiving an input via a processor of the computing device. The input corresponds to data to be transmitted. The method further includes encoding the data to generate spreading codes corresponding at least in part to the data. The method further includes mapping the spreading codes to one or more frequency subcarriers of a plurality of frequency subcarriers, generating a transmit signal based at least in part on the one or more frequency subcarriers, and transmitting the transmit signal via an electrode capacitively coupled to a physical body. The transmit signal is transmitted from the electrode through the physical body.

Abstract: A modulation format estimation device 100 includes: a frequency shift correction unit 112 configured to estimate the amount of a frequency shift using a baseband signal acquired from a received signal and correct the baseband signal based on an estimation result; a frequency error generation unit 122 configured to generate a plurality of frequency errors from a range set based on an error occurring in the estimation of the frequency shift amount; a frequency error introduction unit 123 configured to acquire learning baseband signals in which each of a plurality of source signals modulated by different modulation formats is frequency-shifted by each frequency error; and a modulation format estimation unit 113 configured to input a corrected baseband signal to a first machine learning model created by machine learning using learning data including the plurality of learning baseband signals and a label, and estimate a modulation format of the received signal.

Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

Abstract: An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

Abstract: The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

Abstract: A synchronization timing detector includes n correlators, a calculation unit, and a symbol timing estimating unit. The n correlators calculate and output correlation values, between a received signal oversampled m times for one symbol period and a known synchronization pattern, by shifting sample timings by m/n samples each, where m is a natural number, and n is a natural number that satisfies 3?n?m and is a divisor of m. The calculation unit generates n correlation value vectors by arranging the correlation values output from the n correlators on polar coordinates at intervals of an angle of 2?(n/m) radians, and adds the n correlation value vectors to calculate an angle of a resultant vector of the correlation value vectors. The symbol timing estimating unit estimates a symbol timing of the received signal based on the angle of the resultant vector calculated by the calculation unit.

Abstract: A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Abstract: Apparatuses, systems, and methods for transmitting and multiplexing chirp signals for communications are provided. An example apparatus includes an antenna, a radio, and processing circuitry. The radio may be configured to transmit and receive wireless communications via the antenna, and the processing circuitry configured to establish a wireless communications link with a receiving communications device. The signaling transmitted by the antenna via the radio as controlled by the processing circuitry may include a plurality of sequenced chirp signals within an orthogonal frequency division multiplexing (OFDM) framework.

Abstract: A transmitter 10B always transmits a signal (data in which a dock is embedded) generated by the serializer 11 to the communication link. The receiver 20B includes a recovery circuit 22, a deserializer 23, a selector 25, and a training signal generator 32. The training signal generator 32 generates and outputs a training signal for frequency synchronization of the recovering operation of the recovery circuit 22. The selector 25 receives the signal from the transmitter 10B via the communication link and receives the training signal output from the training signal generator 32. The selector 25 selects and outputs either the received signal or the training signal according to the level of the lock signal output from the recovery circuit 22.

Abstract: The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

Abstract: An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Abstract: An apparatus comprises an RF receiver for receiving an RF signal. The RF receiver includes front-end circuitry to generate a first down-converted signal, and a plurality of signal detectors to generate a corresponding plurality of detection signals from signals derived from the down-converted signal. The RF receiver further includes a controller to provide at least one control signal to the front-end circuitry based on the plurality of detection signals.

Abstract: A communication quality estimating device estimates an error rate of a signal with FEC capable of correcting K errors. The device obtains a frequency measurement value that indicates a frequency at which a codeword including m errors is received. The device determines a transition probability and a continuation probability included in each of a plurality of formulae, such that a frequency calculation value that is calculated using the plurality of formulae and indicates a frequency at which a codeword including m errors is received is brought close to the frequency measurement value. The device calculates a frequency at which a codeword including more than K errors is received, by using the plurality of formulae each with the determined transition probability and the determined continuation probability. The device estimates after-FEC error rate based on a result of the calculation.

Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.