Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: Embodiments of the present invention relate to the field of circuit technology, and disclose a method for correcting a SOC of a battery pack, a battery management system, and a vehicle. The method for correcting an SOC of a battery includes: determining, when a charging process of the battery pack starts, whether an initial SOC value of the battery pack is less than or equal to a preset electricity quantity threshold; when the initial SOC value of the battery pack is less than or equal to the preset electricity quantity threshold, recording state information of the battery pack during the charging process, and generating a differential capacity curve of the battery pack according to the state information; correcting a current SOC value of the battery pack according to the differential capacity curve and a voltage-SOC reference curve of a non-decay zone of the battery pack.

Abstract: A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the marker layer is determined to exist. The marker layer, which is not stored in the connect database, designates a connection between at least a pair of nets in the circuit design.

Abstract: Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a transistor device of the plurality of transistor devices creates a design rule violation, determining whether a force mode input has been received. The example method further includes, responsive to determining that the force mode input has been received, enabling routing of the first connection input.

Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

Abstract: A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

Abstract: In execution of an equalization process between a plurality of cells connected in series, power supply system is provided. In power supply system, control circuit performs active balancing between a plurality of cells included in each of a plurality of series cell groups, using a plurality of active cell balancing circuits, and performs passive balancing between the plurality of series cell groups. Voltage detection circuit connected to a series cell group being undergoing the passive balancing and consuming power is supplied with power from first power supply circuit. Voltage detection circuit connected to series cell group being undergoing active cell balancing by active cell balancing circuit is supplied with power from second power supply circuit higher in efficiency than first power supply circuit.

Abstract: A transportation refrigeration unit including: at least one component powered by an energy storage device composed of a first energy storage pack and a second energy storage pack, wherein the at least one component draws electrical power from the energy storage device at an operating power; a return air temperature sensor to detect a return air temperature; a controller to adjust the operating power in response to the return air temperature, wherein the controller determines a state of charge of the first energy storage pack and a state of charge of the second energy storage pack, wherein the controller selects at least one of the first energy storage pack and the second energy storage pack to power the at least one component in response to the operating power, the state of charge of the first energy storage pack, and the state of charge of the second energy storage pack.

Abstract: Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.

Abstract: Manufacturing a semiconductor chip based on redefining tolerance rules to create an otherwise prohibited structure including redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and fabricating the minimum area metal trench structure on the semiconductor substrate based on the redefined tolerance rule.

Abstract: According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: Provided by the present application are a Direct Current (DC) micro-grid system, a charging loop circuit and a control method thereof. The charging loop circuit selectively connects a charging loop to a first side loop or a second side loop through a set of switches.

Abstract: System and method that to shape micro-object density distribution (how densely the micro-objects are assembled in particular spatial regions) are provided. A high speed camera tracks existing object density distribution. An array of photo-transistor-controlled electrodes is used to generate a dynamic potential energy landscape for manipulating objects with both DEP and EP forces, and a video projector is used actuate the array. One or more computing devices are used to: process images captured by the camera to estimate existing density distribution of objects; receive a desired density distribution of micro-objects; define a model describing a variation of micro-object density over time due to capacitance-based interactions; generate a sequence of electrode potential that when generated would minimize error between the existing density distribution and a desired density distribution; and use the sequences of electrode potentials to actuate the electrodes.

Abstract: A method for determining a perturbation energy of a quantum state of a many-body system includes constructing a wave function that approximates the quantum state by adjusting parameters of the wave function to minimize an expectation value of a zeroth-order Hamiltonian. The zeroth-order Hamiltonian explicitly depends on a finite mass of each of a plurality of interacting quantum particles that form the many-body system, the quantum state has a non-zero total angular momentum, the wave function is a linear combination of explicitly correlated Gaussian basis functions, and each of the explicitly correlated Gaussian basis functions includes a preexponential angular factor. The perturbation energy is calculated from the wave function and a perturbation Hamiltonian that explicitly depends on the finite mass of each of the plurality of interacting quantum particles. The perturbation energy may be added to the minimized expectation value to obtain a total energy of the quantum state.

Abstract: Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.

Abstract: A method for converting a lineless table into a lined table includes associating a first set of tables with a second set of tables to form a set of multiple table pairs that includes tables with lines and tables without lines. A conditional generative adversarial network (cGAN) is trained, using the table pairs, to produce a trained cGAN. Using the trained cGAN, lines are identified for overlaying onto a lineless table. The lines are overlaid onto the lineless table to produce a lined table.

Abstract: The present invention provides a cover (201, 220, 230) for removably attaching to a mobile device (101, 117) with an antenna (118), comprising a battery (204), which is configured to provide electrical supply power, an electrical contacting element (205, 206, 211), which is configured to electrically couple the battery (204) to the antenna (118) of the mobile device (101, 117), and a blocking filter (207), which is coupled between the electrical contacting element (205, 206, 211) and the battery (204) and which is configured to block RF signals from the electrical contacting element (205, 206, 211) to the battery (204) and to allow transmission of the electrical supply power between the battery (204) and the electrical contacting element (205, 206, 211). Further, the present invention provides a corresponding mobile device (101, 117) and a corresponding method.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.