Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.

Abstract: A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

Abstract: A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.

Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile by determining a number acid generators and quenchers within a photoresist volume, determining a number of photons absorbed by the photoresist volume, determining a number of the acid generators converted to acid, determining a number of acid and quencher reactions within the photoresist volume, calculating a development of the photoresist volume, producing with the processor a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume, and measuring the dimensional properties of the photoresist profile.

Abstract: A system and method for charging a chargeable device is provided. The system can include a wireless charger including a wireless power antenna and a wireless power transmitter coupled to the wireless power antenna and configured to generate a wireless charging field in at least one charging region. The wireless charging field includes a plurality of power signals. The wireless charger further includes a communication antenna and a transceiver coupled to the communication antenna and configured to communicate with the chargeable device via the communication antenna. The wireless charger further includes a controller configured to facilitate avoidance of cross connection of the chargeable device with the wireless charger and at least one other wireless charger in which the chargeable device receives power from the wireless power transmitter of the wireless charger while communicating with at least one other wireless charger.

Abstract: A control circuit for reducing a charging time and a method thereof are provided. The charging device includes an input unit configured to receive a control signal indicating that applied power is process power, and a switch configured to cut off a path between a terminal set and a battery while the process power is applied, when the applied power is the process power.

Abstract: Embodiments of the present invention include control methods employed in multiphase distributed energy storage systems that are located behind utility meters typically located at, but not limited to, medium and large commercial and industrial locations. These distributed energy storage systems can operate semi-autonomously, and can be configured to develop energy control solutions for an electric load location based on various data inputs and communicate these energy control solutions to the distributed energy storage systems. In some embodiments, one or more distributed energy storage systems may be used to absorb and/or deliver power to the electric grid in an effort to provide assistance to or correct for power transmission and distribution problems found on the electric grid outside of an electric load location. In some cases, two or more distributed energy storage systems are used to form a controlled and coordinated response to the problems seen on the electric grid.

Abstract: A method for dynamically charging an electrically powered apparatus includes receiving a selection of a charging mode from a user, such that the selected charging mode is a fast charging mode or a slow charging mode. The method also includes dynamically scheduling a charging mode for charging the apparatus according to the selected charging mode and a status of a fast charging module, and electrically charging the apparatus according to the dynamically scheduled charging mode.

Abstract: The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.

Abstract: A vehicle charging unit includes a lid box inserted into a first hole in the body of a vehicle from outside of the vehicle and attached to the body, and an inlet fixed to the lid box. The lid box includes an attachment portion, a bottom having a second hole formed therein, and a sidewall. The bottom has a stud bolt protruding toward inside of the vehicle in a state in which the lid box is attached to the body. The inlet includes a barrel portion capable of receiving a charge connector from outside of the vehicle and a collar portion positioned around the barrel portion. The barrel portion is inserted into the second hole from inside of the vehicle and the collar portion is fixed with the stud bolt, whereby the inlet is fixed to the lid box.

Abstract: Embodiments of the present invention relate to a portable charging case that can serve as both a charging base and a protective carrying case for a rechargeable stylus. The portable charging case can enable a quick connect and release of the stylus using magnetic force for magnetic engagement of the stylus to the charging base. The charging base may include a logic board that dynamically changes the polarity of the charge coming in through the charging base charging contacts. Such a dynamic change of polarity can recharge the stylus irrespective of the polarity alignment between the stylus charging terminals and the charging base charging contacts.

Abstract: A system is provided for performing recharging and data communication. The system includes a terminal and a connection device that connects the terminal and an external device, and that selectively provides the terminal with a recharging function, a data communication function, and a recharging and data communication function, according to a type of the connected external device. The terminal determines the type of the connected external device based on a voltage received from the connection device, when the terminal is connected to the connection device, and selectively operates in a recharging mode, a data communication mode, and a recharging and data communication mode based on the type of the connected external device.

Abstract: An adapter includes a signal generation unit. By connection between the adapter and a plug of a charging cable used when performing external charging with electric power from an external power supply, the signal generation unit supplies a signal instructing power feeding to a vehicle. In response to the signal instructing power feeding, the vehicle drives a power conversion device, thereby supplying electric power from the vehicle to an external electrical device through the charging cable.

Abstract: Performance analysis for an electronic system includes determining, using a processor, data traffic patterns stored within a core library of an electronic design automation system, wherein the data traffic patterns are part of cores stored within the core library. The determined data traffic patterns are displayed using a display as modeling options. A user input selecting a displayed data traffic pattern is received; and the selected data traffic pattern is executed as part of modeling the electronic system.

Abstract: A charging system includes a transmission line, a power adaptor, and an electronic device. The transmission line includes a first terminal and a second terminal. The power adaptor is coupled to the first terminal and generates a charging voltage and a first voltage signal. The charging voltage is at a first voltage level. The electronic device is coupled to the second terminal and receives the first voltage signal. When the first voltage signal is larger than a first preset voltage signal, the electronic device outputs a second voltage signal to the power adaptor. When the second voltage signal is larger than a second preset voltage signal, the power adaptor adjusts the charging voltage into a second voltage level.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.