Patents Examined by Binh Tat
  • Patent number: 9331486
    Abstract: An exemplary method and apparatus for detecting islanding conditions of a distributed grid are disclosed, wherein transfer of power through a power electrical unit is controlled on the basis of a control reference. The apparatus includes a first stage and a second stage performing a respective portion of the method. The first stage injects a reactive component to the control reference, and, for at least one electrical quantity of the grid, determines a change in the quantity induced by the injected component, and determines, on the basis of the change in the electrical quantity, whether to move to the second stage of the method.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: May 3, 2016
    Assignee: ABB RESEARCH LTD
    Inventors: Gerardo Escobar, Sami Pettersson, Leonardo-Augusto Serpa, Ngai-Man Ho, Antonio Coccia, Alexandre Oudalov, Adrian Timbus
  • Patent number: 9331610
    Abstract: An electromotive furniture drive includes an electric motor, the rotational direction of which can be reversed, a motor controller, a manual control, a battery unit, and a mains power supply device. A speed-reducing transmission is connected downstream of the electric motor and a further transmission is connected downstream of each speed-reducing transmission and the battery unit has at least one battery. To enable simple, economical and easy installation, in particular in tight installation spaces, the furniture drive has a coupling device which includes a charging device for charging the at least one battery of the battery unit. The coupling device also has a reference device, which is connected to a charging device The furniture drive is especially suited for slatted bed frames and armchairs.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 3, 2016
    Assignee: DEWERTOKIN GMBH
    Inventor: Armin Hille
  • Patent number: 9330221
    Abstract: Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 3, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Jongwook Kye, Harry J. Levinson
  • Patent number: 9330229
    Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate a first verified data. The processor performs a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate second verified data according to the reference layout data. The processor performs a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed. The processor performs a Boolean check on the third verified data to generate fourth verified data using the reference layout data.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Chih Chang, Kuo-Hsun Huang, Chao-Yao Chiang
  • Patent number: 9330217
    Abstract: Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 3, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Yanhua Yi, Jun Zhao
  • Patent number: 9327610
    Abstract: A system and method for individually discharging battery cells in a high voltage vehicle battery. The system includes a battery controller that monitors and controls the state-of-charge of each of the battery cells and a cell balancing circuit for maintaining the charge of the cells substantially equal. The controller receives a signal from a vehicle crash detector indicating that the vehicle has been in a crash, and in response instructs the cell balancing circuit to discharge all of the battery cells.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 3, 2016
    Assignee: GM Global Technology Operations LLC
    Inventors: Peter Andres, Ryan M. Frakes, Paul W. Kelley
  • Patent number: 9321433
    Abstract: A method of quickly supplying electric energy to electric vehicles and the power supply device thereof are provided. The method includes providing a rechargeable battery pack on an electric vehicle and providing a battery replacement device, a charging room and a battery storeroom in a power exchange station. The rechargeable battery pack includes a battery box and standardized standard battery units. The standard battery units are located in the battery box during operation, and are capable of being smoothly loaded into and unloaded from the battery box along the guiding rails. The rechargeable battery pack is pre-installed in the electric vehicle and the drained standard battery units within the battery box are replaced with fully-charged standard battery units upon payment when the electric vehicle in need of electric power supply is driven into the power exchanging station.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: April 26, 2016
    Inventors: Xuejun Yin, Xiangfei Kong, Boting Yin
  • Patent number: 9323876
    Abstract: Pre-boot metadata transfer may include loading a first configuration bitstream into a programmable integrated circuit (IC), wherein the first configuration bitstream includes a first circuit design and metadata for a second circuit design. The metadata may be stored within a memory of the programmable IC. A configuration bitstream load condition may be detected and, responsive to the configuration bitstream load condition, a second configuration bitstream may be loaded into the programmable IC. The second configuration bitstream includes a second circuit design.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: April 26, 2016
    Assignee: XILINX, INC.
    Inventors: Patrick Lysaght, Yi-Hua E. Yang, Paul R. Schumacher, Graham F. Schelle
  • Patent number: 9325180
    Abstract: A power supply system effective to provide power to a plurality of different personal electronic devices includes a source of AC or DC power, a power converter effective to convert the AC or DC power to a useable voltage and amperage, a remote power outlet or a plurality of remote power outlets each configured to receive one or more connectors and a signal decoder. The signal decoder determines the requirements of a connected one of the personal entertainment devices and personal computing devices and apply the requirements to the power outlet for powering the device.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 26, 2016
    Assignee: Astronics Advanced Electronic Systems Corp.
    Inventors: Mark A. Peabody, Jeffrey A. Jouper
  • Patent number: 9302591
    Abstract: One aspect provides a wireless power transmitter. The wireless power transmitter includes a transmit antenna configured to generate a field for wireless transmit power in both a first and second configuration. The wireless power transmitter further includes a first capacitor. The wireless power transmitter further includes at least one switch configured to selectively connect the first capacitor in one of the first and second configuration. The first capacitor can be in series with the transmit antenna in the first configuration and in parallel with the transmit antenna in the second configuration.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chang-Yu Huang, Jonathan Beaver, Nicholas Athol Keeling, Mickel Bipin Budhia, Michael Le Gallais Kissin
  • Patent number: 9296349
    Abstract: An electrical powered vehicle is equipped with a coil unit capable of receiving electric power from a facility self-resonant coil external to the vehicle. The electrical powered vehicle includes: a pair of side members aligned in a widthwise direction of the vehicle and extending in a fore-aft direction of the vehicle; a vehicle self-resonant coil coupled with the facility self-resonant coil resonantly via an electromagnetic field to be capable of at least one of transmitting electric power and receiving electric power; and a vehicle capacitor provided to the vehicle self-resonant coil between the paired side members.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: March 29, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru Nakamura, Shinji Ichikawa
  • Patent number: 9298874
    Abstract: Various features pertain to circuit design schemes that route wires based on temperature. In one aspect, time-variant temperature conditions along a prospective route are taken into account when determining whether to use the route for a wire. For example, a route can be selected from among a set of prospective two-dimensional (2-D) or three-dimensional (3-D) routes based on which route is associated with the “smoothest” temperature gradient. Other aspects of the disclosure pertain to determining or exploiting adjustable search windows, layer wiring densities, worst-case skew values and resistance-capacitance (RC) coupling characteristics, particularly for use with 3-D routing within the layers of a stacked multi-layer substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: March 29, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chun-Chen Liu, Shengqiong Xie
  • Patent number: 9292627
    Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Patent number: 9292642
    Abstract: Systems and methods are provided for physical layout of superconductor circuits. The physical layout system and method is configured to place and route the superconducting circuits by first placing the gates in the form of gate tiles within unoccupied areas of a predetermined circuit design based on a netlist. Each gate tile type includes a particular gate type and a plurality of unassigned Josephson junctions that can be employed in the gates and/or the active interconnects. Inductive wires are then routed between gates incorporating and assigning the Josephson junctions to produce active interconnects between the I/O terminals of the gates based on connections defined in the netlist.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 22, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Anna Y. Herr, Quentin P. Herr
  • Patent number: 9293408
    Abstract: In one embodiment, an integrated circuit has a conductive layer, where the conductive layer has a first set of regions and a second set of fill material regions, and the second set of fill material regions has a line of symmetry. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: March 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Hongmei Liao
  • Patent number: 9285796
    Abstract: Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: March 15, 2016
    Assignee: Synopsys, Inc.
    Inventors: Igor L. Markov, Kenneth S. McElvain
  • Patent number: 9286428
    Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni, Sourav Saha
  • Patent number: 9287719
    Abstract: Power supply side equipment comprises a high-frequency power supply, a matching box, a primary side resonance coil, an output impedance variable unit, a matching state detection unit, and a control unit. By a magnetic field resonance, the primary side resonance coil transmits power in a non-contact manner to a load through a secondary side resonance coil. At least the matching box, the primary side resonance coil, the secondary side resonance coil, and the load constitute a resonance system having a resonant frequency. The matching state detection unit detects the matching state between the input impedance of the resonance system and the output impedance of the high-frequency power supply at the resonant frequency. The control unit adjusts the output impedance variable unit and the matching box according to the detection result by the matching state detection unit so that the input impedance of the resonance system and the output impedance of the high-frequency power supply match each other.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toyota Jidoshokki and Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroshi Katsunaga, Yukihiro Yamamoto, Koji Nakamura, Shinji Ichikawa, Toru Nakamura
  • Patent number: 9280627
    Abstract: A system and method that implement an object-oriented model for requirements of a hardware design in order to verify the design. The object-oriented model abstractly captures the design topology, capability, control, and status of the design. An object-oriented model or definition of a hardware design is based on one or more specifications or standards implemented with the design. With the object-oriented model, a system and method for storing and displaying data captured during a test run is implemented. Graphical displays are defined to show run information for abstract objects of the design. Predefined graphical displays may be altered to accommodate the features of the object-oriented model and new graphical displays may be defined for objects in the model.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 8, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Tal Tabakman, Yonatan Ashkenazi, Nir Paz, Yochi Bilitski
  • Patent number: 9275173
    Abstract: A method, apparatus and program product automatically generate a grayscale lithography mask file (76) from a three dimensional (3D) model (72) of a desired topography, e.g., as generated by a three dimensional computer aided design (CAD) tool (70).
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: March 1, 2016
    Assignee: University of Louisville Research Foundation, Inc.
    Inventors: James Loomis, Curtis McKenna, Kevin M. Walsh