Patents Examined by Bitew A Dinke
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Patent number: 11832459Abstract: The invention relates to methods for producing a light-absorbing material with a perovskite-like structure, and can be used to form a light-absorbing layer in the production of photovoltaic cells for saving the materials and increasing the allowable size of converters. These advantages are achieved by forming a uniform layer of component B on the substrate, preparing a mixture of reagents that react with component B under predetermined conditions, and a reaction inhibitor that suppresses this reaction under these conditions; the prepared mixture is applied in stoichiometric amount or greater than stoichiometric on the layer of component B and the reaction inhibitor is removed from the mixture, ensuring activation of the chemical reaction between the mixture of reagents and component B to form films of perovskite-like material.Type: GrantFiled: December 18, 2018Date of Patent: November 28, 2023Assignee: JOINT STOCK COMPANY KRASNOYARSK HYDROPOWER PLANTInventors: Evgenij Alekseevich Gudilin, Aleksej Borisovich Tarasov, Andrej Andreevich Petrov, Nikolaj Andreevich Belich, Aleksej Yur'evich Grishko
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Patent number: 11823898Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.Type: GrantFiled: December 11, 2020Date of Patent: November 21, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yuichi Onozawa
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Patent number: 11818943Abstract: Organic light-emitting diodes are disclosed comprising an electron transport layer and a hole transport layer. At least one of the transport layers is formed by (a) dissolving tubulin or microtubules in a mixture of water and a solvent that changes the surface charge of tubulin, wherein the percentage of solvent in the mixture is selected so that the tubulin acquires a desired surface charge, and (b) using the tubulin with the desired surface charge to fabricate the at least one of the transport layers. Advantageously, the solvent may be DMSO. Methods of fabricating such organic light emitting diodes are also disclosed.Type: GrantFiled: June 22, 2021Date of Patent: November 14, 2023Assignee: Novocure GmbHInventors: Aarat Pratyaksh Kalra, Jack Adam Tuszynski, Sahil Deepak Patel, Karthik Shankar
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Patent number: 11817447Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.Type: GrantFiled: August 6, 2020Date of Patent: November 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungjun Song, Hyunkwang Jeong, Changsu Kim, Chanhee Jeon
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Patent number: 11803160Abstract: There is provided a solar panel including: solar cells each of which is formed in a belt-shape extending in a predetermined direction on a plate-shaped surface and which are disposed in rows in a cell-width direction; a partition area that divides the solar cells from each other; and a connecting part that connects adjoining solar cells among the solar cells electrically in series at respective ends in the extending direction. The solar cells have, across at least two of the solar cells, a transparent power generation area in which a power generation area and a transparent area are alternately disposed in the extending direction. The transparent power generation area extends over an entire cell width of at least one of the solar cells, and the connecting part is disposed at each of opposite ends in the extending direction of the at least one solar cell.Type: GrantFiled: March 12, 2020Date of Patent: October 31, 2023Assignee: CASIO COMPUTER CO., LTD.Inventor: Yuta Saito
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Patent number: 11791267Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.Type: GrantFiled: June 7, 2021Date of Patent: October 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jinho Park, Shaofeng Ding, Yongseung Bang, Jeong Hoon Ahn
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Patent number: 11784161Abstract: A system includes an image sensor structure and a flow cell. The image sensor structure includes an image layer disposed over a base substrate. A device stack is disposed over the image layer. A bond pad is disposed in the device stack. A passivation stack is disposed over the device stack and the bond pad. An array of nanowells is disposed in a top layer of the passivation stack. A through-silicon via (TSV) is in electrical contact with the bond pad. The TSV extends through the base substrate. A redistribution layer (RDL) is disposed on a bottom surface of the base substrate. The RDL is in electrical contact with the TSV. The flow cell is disposed upon the top layer of the passivation stack to form a flow channel therebetween. The flow channel is disposed over the array of nanowells and the bond pad.Type: GrantFiled: November 2, 2020Date of Patent: October 10, 2023Assignee: ILLUMINA, INC.Inventors: Tracy Helen Fung, Hai Quang Tran
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Patent number: 11777048Abstract: A sensor includes a first electrode, a second electrode facing the first electrode, and a light absorbing layer between the first electrode and the second electrode. The light absorbing layer may have a first absorption spectrum having a first absorption peak in a first infrared wavelength region and a second absorption peak in a second infrared wavelength region, the second infrared wavelength region being a longer wavelength region than the first infrared wavelength region. The second absorption spectrum does not at least partially overlap with the first absorption spectrum. The second absorption spectrum may have a lower absorption intensity than the first absorption spectrum. An external quantum efficiency (EQE) spectrum that is amplified in the second infrared wavelength region is exhibited in the sensor.Type: GrantFiled: April 21, 2021Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Seok Leem, Rae Sung Kim, In Sun Park, Ohkyu Kwon, Changki Kim
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Patent number: 11777049Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.Type: GrantFiled: August 27, 2020Date of Patent: October 3, 2023Assignee: Artilux, Inc.Inventors: Yen-Cheng Lu, Yun-Chung Na
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Patent number: 11769782Abstract: A solid-state imaging element including a photoelectric conversion layer of a first electrical conductivity type including a plurality of pixel regions, an electrode electrically coupled to the photoelectric conversion layer and provided for each of the pixel regions, a semiconductor layer provided between the electrode and the photoelectric conversion layer and having a bandgap larger than a bandgap of the photoelectric conversion layer, a diffusion part disposed in a vicinity of an edge of the pixel region and including an impurity of a second electrical conductivity type that is diffused from the semiconductor layer across the photoelectric conversion layer, and a non-diffusion part provided inside the diffusion part and not including the impurity of the second electrical conductivity type in the photoelectric conversion layer.Type: GrantFiled: April 8, 2019Date of Patent: September 26, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shunsuke Maruyama, Hideki Minari
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Patent number: 11765879Abstract: A substrate processing apparatus according to an aspect of the present disclosure includes a mounting section on which a substrate is placed, a structure member provided above the mounting section so as to face the mounting section, and an optical sensor. The optical sensor is configured to detect a height of the mounting section, a height of the structure member, and a height of the substrate, by emitting light from above the structure member to a predetermined location of the mounting section, a predetermined location of the structure member, and the substrate, and by receiving reflection light from the mounting section, the structure member, and the substrate.Type: GrantFiled: May 7, 2020Date of Patent: September 19, 2023Assignee: Tokyo Electron LimitedInventor: Junnosuke Taguchi
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Patent number: 11756931Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.Type: GrantFiled: August 3, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 11705530Abstract: An imaging device includes a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked. A semiconductor material layer including an inorganic oxide semiconductor material having an amorphous structure at least in a portion is formed between the first electrode and the photoelectric conversion layer, and the formation energy of an inorganic oxide semiconductor material that has the same composition as the inorganic oxide semiconductor material having an amorphous structure and has a crystalline structure has a positive value.Type: GrantFiled: April 10, 2019Date of Patent: July 18, 2023Assignee: SONY CORPORATIONInventors: Hiroshi Nakano, Toshiki Moriwaki
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Patent number: 11688730Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.Type: GrantFiled: April 8, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
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Patent number: 11657953Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: April 14, 2021Date of Patent: May 23, 2023Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Patent number: 11652121Abstract: A color separation element and an image sensor including the same are disclosed. The color separation element includes a spacer layer, and a color separation lens array including at least one nano-post provided in the spacer layer to control a phase distribution of incident light so that light having the same wavelength of the incident light is multi-focused on a plurality of target regions; and periodic regions in which the phase distribution control layer is repeatedly arranged.Type: GrantFiled: November 25, 2020Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sookyoung Roh, Seokho Yun, Hongkyu Park, Minwoo Lim
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Patent number: 11646291Abstract: A method for calibrating a second bonding machine based on a calibrated first bonding machine is disclosed. The first bonding machine includes a first ultrasonic transducer. The second bonding machine includes a second ultrasonic transducer and a power supply. The method includes providing a first electrical calibration supply that causes the first ultrasonic transducer to oscillate at a first calibration amplitude when it is damped by a mechanical damping, providing a second electrical calibration supply that causes the second ultrasonic transducer to oscillate at the same calibration amplitude when it is damped by the same mechanical damping.Type: GrantFiled: July 31, 2019Date of Patent: May 9, 2023Assignee: Infineon Technologies AGInventors: Florian Eacock, Michal Chajneta, Stefan Tophinke
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Patent number: 11622665Abstract: A household appliance includes a housing; a treating chamber located within the housing and having an access opening; a closure element movable relative to the access opening between opened and closed positions to selectively provide access to the treating chamber through the access opening; a controller associated with the housing and implementing a treating cycle on at least one item in the treating chamber; and a human-machine interface. The HMI includes a first portion associated with the housing and a second portion associated with the closure element. The first portion includes non-touch sensitive indicia. The second portion includes an electrically conductive layer having a touch-sensitive area corresponding to the indicia of the first portion and is arranged to be in register with a corresponding selection area when the closure element is in the closed position.Type: GrantFiled: December 18, 2020Date of Patent: April 11, 2023Assignee: Whirlpool CorporationInventors: Darryl C. Bodine, Randell L. Jeffery, Eric Schuh
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Patent number: 11621366Abstract: A passivation process includes the successive steps of a) providing a stack having, in succession, a substrate based on crystalline silicon, a layer of silicon oxide, and at least one layer of transparent conductive oxide; and b) applying a hydrogen-containing plasma to the stack, step b) being executed at a suitable temperature so that hydrogen atoms of the hydrogen-containing plasma diffuse to the interface between the substrate and the layer of silicon oxide.Type: GrantFiled: June 30, 2020Date of Patent: April 4, 2023Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Raphael Cabal, Bernadette Grange
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Patent number: 11616154Abstract: Various processes can apply pressure and/or heat to a photovoltaic (PV) layer, including processes that integrate solar cells into different types of industrial glass such as an autoclave lamination process. The disclosure describes a planarization technique that can be used on the PV layer to eliminate point loads caused by such processes. In an aspect, a method for producing a component is described that includes disposing or placing a planarization material on a PV layer, modifying a physical form of the planarization material to provide a planar surface made of the planarization material on one side of the PV layer having surface irregularities, and forming a stack of layers (e.g., as part of an autoclave lamination process) for the component by disposing a first layer over the planar surface on the one side of the PV layer and a second layer over the other, opposite side of the PV layer.Type: GrantFiled: September 27, 2019Date of Patent: March 28, 2023Assignee: UTICA LEASECO, LLCInventor: Todd Krajewski