Abstract: The invention relates to a process for fabricating at least tensilely strained planar photodiode 1, comprising producing a stack formed from a semiconductor layer 53, 55 made of a first material and from an antireflection layer 20; producing a peripheral trench 30 that opens onto a seed sublayer 22 made of a second material of the antireflection layer 20; epitaxy of a peripheral section 31 made of the second material in the peripheral trench 30; and returning to room temperature, a detecting section 10 then being tensilely strained because of the difference in coefficients of thermal expansion between the two materials.

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

Abstract: A semiconductor package structure includes a carrier, an electronic device, a spacer, a transparent panel, and a conductive wire. The electronic device has a first surface and an optical structure on the first surface. The spacer is disposed on the first surface to enclose the optical structure of the electronic device. The transparent panel is disposed on the spacer. The conductive wire electrically connects the electronic device to the carrier and is exposed to air.

Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.

Abstract: Some embodiments of the present BOP control systems include a system controller configured to actuate a first BOP function by communicating one or more commands to one or more nodes of a functional pathway selected from one or more available functional pathways associated with the first BOP function, each node comprising an actuatable component configured to actuate in response to a command received from the system controller, each node having one or more sensors configured to capture a first data set corresponding to actuation of the component and a processor configured to analyze the first data set to determine a useful life remaining of the component and/or compare the first data set to a second data set corresponding to a simulation of actuation of the component.

Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.

Abstract: According to one embodiment, a variable resistance element includes a first electrode, a second electrode, and a variable resistance layer and a tellurium-containing compound layer disposed between the first electrode and the second electrode. The tellurium-containing compound layer contains tellurium, oxygen, and at least one element selected from tin, copper, and bismuth. In some examples, the tellurium-containing compound layer can function as a switching layer in a memory cell structure.

Abstract: A plurality of light-emitting devices (10) include a plurality of light-emitting devices (10a), a plurality of light-emitting devices (10b), and a plurality of light-emitting devices (10c). The plurality of light-emitting devices (10) are aligned on a reflecting member (20). Six light-emitting devices (10c) are aligned in a straight line along one direction. Four light-emitting devices (10b) are aligned surrounding a region facing one ends of the six light-emitting devices (10c). Each of four light-emitting devices (10a) are aligned with each of the four light-emitting devices (10b) outside the four light-emitting devices (10b).

Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.

Abstract: A method includes forming a dielectric cap over a semiconductor substrate; forming a dummy gate structure over the dielectric cap; forming gate spacers on opposite sidewalls of the dummy gate structure and on a top surface of the dielectric cap; removing the dummy gate structure to form a gate trench between the gate spacers and exposing the dielectric cap; and performing an ion implantation to form a doped region in the semiconductor substrate through the dielectric cap.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: A photo-sensing device includes a semiconductor substrate, a photosensitive device, a dielectric layer and a light pipe. The photosensitive device is in the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The light pipe is over the photosensitive device and embedded in the dielectric layer. The light pipe includes a curved and convex light-incident surface.

Abstract: An image sensor (32) includes a plurality of pixel sensing portion (320) that are arranged in columns and rows. Each of the pixel sensing portions (320) includes a thin film transistor (11), and a photodetection diode (13) including n-type (16), intrinsic (15), and p-type semiconductor layers (14). The intrinsic semiconductor layer (15) of the photodetection diode (13) of each of the pixel sensing portions (320) has a crystallinity gradient that varies from an amorphous silicon structure to a microcrystalline silicon structure along a first direction (L1) extending from the p-type semiconductor layer (14) toward the n-type semiconductor layer (16). An image sensing-enabled display apparatus (3) and a method of making the image sensor (32) are also disclosed.

Abstract: A light-emitting device includes: a semiconductor stacked body comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked in this order; a first insulating film that covers the active layer and the second conductive semiconductor layer; a first conductive layer that continuously surrounds a lateral surface of the first conductive semiconductor layer that is exposed from the first insulating film; a second insulating film that covers the first conductive layer, the active layer, and the second conductive semiconductor layer and that has a hole disposed above the second conductive semiconductor layer; and a second conductive layer that continuously covers, via the second insulating film, an end portion of the first conductive layer located in proximity to an end portion of the second conductive semiconductor layer, wherein the second conductive layer is connected to an upper surface of the second conductive semiconductor layer through the hole.

Abstract: The load force bolster assembly includes a metallic stiffener. A carrier associated with a CPU (Central Processing Unit) is located upon the load force bolster assembly and positioned upon the electrical connector. A heat sink is located upon both the carrier and the load force bolster assembly wherein a torsioned wire of the bolster assembly provides a downward force upon an up-and-down movable stud which is secured to a screw of the heat sink so as to downwardly push the heat sink, thus enhancing the normal forces among the heat sink, the CPU and the contacts of the electrical connector. To efficiently hold the torsioned wire in position around a bottom corner of the stiffener, a retention groove is formed around the top portion of the restricting pole, and a pressing ring is downwardly snapped into the retention groove so as to restrain the torsioned wire in position.

Abstract: Techniques, systems, and devices are disclosed for implementing a photoconductive device performing bulk conduction. In one exemplary aspect, a photoconductive device is disclosed. The device includes a light source configured to emit light; a crystalline material positioned to receive the light from the light source, wherein the crystalline material is doped with a dopant that forms a mid-gap state within a bandgap of the crystalline material to control a recombination time of the crystalline material; a first electrode coupled to the crystalline material to provide a first electrical contact for the crystalline material, and a second electrode coupled to the crystalline material to provide a second electrical contact for the crystalline material, wherein the first and the second electrodes are configured to establish an electric field across the crystalline material, and the crystalline material is configured to exhibit a substantially linear transconductance in response to receiving the light.

Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: The present disclosure relates to the field of manufacturing displays, and provides a method for manufacturing a display substrate, a method for manufacturing a mask plate, and a display device. The method for manufacturing a display substrate comprises: providing a first substrate; providing a mask plate opposite to the first substrate, the mask plate comprising one or more light-transmissive regions, and an electrically conductive material is provided on a surface of the mask plate facing the first substrate; and irradiating a surface of the mask plate facing away from the first substrate with light rays, such that the electrically conductive material is transferred to a surface of the first substrate facing the mask plate, thereby forming an electrically conductive layer having one or more electrically conductive portions, wherein a projection of each of the one or more electrically conductive portions on the mask plate coincides with a respective light-transmissive region.

Abstract: The present disclosure provides an image sensor panel (ISP) and a method for fabricating the image sensor panel (ISP). In one aspect, the method includes forming a well in an assembly, forming a bottom electrode in the well, forming a photosensitive layer in the well, and forming a top electrode over the photosensitive layer.

Abstract: For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display.