Abstract: The present invention provides a semiconductor device including a first semiconductor element to be bonded to a wiring board in a flip-chip bonding manner, a resin peripheral wall provided on the wiring board in such a manner as to surround the first semiconductor element, a sealing resin poured so as to fill a space surrounded by the resin peripheral wall and then hardened, and a second semiconductor element provided in such a manner that a back surface thereof is fixed on an upper surface of the sealing resin and a electrode provided on a front surface thereof is connected to a segment of wiring on the wiring board by means of a bonding wire, and provides a method of fabricating the semiconductor device.

Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Abstract: A micromechanical device includes a single crystal micromachined micromechanical structure. At least a portion of the micromechanical structure is capable of performing a mechanical motion. A piezoelectric epitaxial layer covers at least a part of said portion of the micromechanical structure that is capable of performing a mechanical motion. The micromechanical structure and piezoelectric epitaxial layer are composed of different materials. At least one electrically conducting layer is formed to cover at least part of the piezoelectric epitaxial layer.

Abstract: A radiation detector is of the type, which by use of electric signals, which indicates the position of an irradiated point on a detector surface of the detector. The detector includes a semiconductor wafer having at least two barrier layers, which are arranged in such manner that when applying an electric bias across the layers, one layer is reversely biased and the other if forwardly biased, the extension of the reversely biased barrier layer substantially coinciding with the detector surface. The detector further includes at least two conductive layers provided with at least one current collecting electrode, the conductive layers being arranged so as to allow a transistor amplification between the forwardly and reversely biased layer by use of charge currents generated by the radiation in the irradiated point and separated by the reversely biased barrier layer.

Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a storage node oxide layer having a hole for forming a storage node on a substrate; forming a silicon layer on the storage node oxide layer having the hole; forming a photoresist on the silicon layer such that the photoresist fills the hole; forming a storage node having a cylinder shape inside of the hole by removing the silicon layer disposed on an upper surface of the storage node oxide layer; ion-implanting an impurity onto head portions of the storage node under a state that the photoresist remains; removing the photoresist; and growing metastable-polysilicon (MPS) grains on inner walls of the storage node.

Abstract: A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.

Abstract: A method of production of a semiconductor device able to utilize a conventional production system for a resin board to thereby produce a wafer level package without increasing the production cost, comprising electrolessly plating the electrode terminals to cover the surfaces of the electrode terminals by a protective film protecting the electrode terminals from laser beams; grinding the back side of the semiconductor wafer to reduce the thickness of the semiconductor wafer before or after forming the protective film; covering the entirety of the electrode terminal forming surface and back side of the semiconductor wafer, having the electrode terminals covered by a protective film and processed to reduce the thickness of the semiconductor wafer, by a resin to form a laminate; and focusing a laser beam toward the electrode terminal forming surface of the semiconductor wafer from outside the laminate to form via holes with the protective film exposed at their bottom surfaces, then filling the via holes by electr

Abstract: A method to selectively deposit a barrier layer on dielectric material that surrounds one or more metal interconnects on a substrate is disclosed. The barrier layer is selectively deposited on the metal film using a cyclical deposition process including a predetermined number of deposition cycles followed by a purge step. Each deposition cycle comprises alternately adsorbing a refractory metal-containing precursor and a reducing gas on the dielectric material formed on the substrate in a process chamber.

Abstract: A silicon-on-insulator structure provides an effective drift field for holes, and simultaneously enhanced recombination centers for holes and electrons. The structure includes a silicon substrate, an oxide insulation layer disposed above the silicon substrate, a silicon body layer disposed above the oxide insulation layer, and a field shield gate disposed above the silicon body layer. The field shield gate includes a conductor portion, and an alumina insulation layer disposed beneath the conductor portion. The oxide insulation layer and the silicon body layer each include at least one channel stop region, and at least one recombination center for the recombination of positive- and negative-charge carriers. The effective drift field and enhanced recombination centers facilitate the rapid recombination of the charge carriers, leading to a very small recombination time constant, which overcomes the floating body effect associated with conventional silicon-on-insulator structures.

Abstract: A tape assembly for use in wafer dicing includes a layer of adhesive dicing tape having a size at least as large as a footprint of a die, and a screening portion which is adhered to the tape. The screening portion is interposed between the layer of tape and the die when the die is adhered to the layer of tape. The screening portion covers an interior portion of the layer of tape. The screening portion is sized and shaped to leave a sufficient portion of the layer of tape underlying a perimeter of the die exposed to adhere the die to the layer of tape.

Abstract: A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile ferroelectric memory device can include first and second split wordlines formed along a first direction on a substrate at prescribed intervals, a first electrode of a first ferroelectric capacitor on the second split wordline and a first electrode of a second ferroelectric capacitor on the first split wordline, first and second ferroelectric layers respectively on surfaces of the first electrodes of the first and second ferroelectric capacitors, and second electrodes of the first and second ferroelectric capacitors, respectively, on surfaces of the first and second ferroelectric layers.

Abstract: A method of manufacturing a semiconductor device is disclosed which comprises, forming a first well region by performing an ion implantation process for implanting first ions into a semiconductor substrate, and then forming a second well region in the first well region by performing an ion implantation process for implanting second ions having larger mass than the first ions; and forming a three-part or three-fold well region by performing an annealing process on the result structure wherein the lighter first ions are disposed in the upper and lower well regions and the heavier second ions are disposed in the middle well region.

Abstract: A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.

Abstract: A display device includes a first substrate provided with first picture electrodes having reflecting parts a second transparent substrate provided with transparent second picture electrodes, with pixels at areas of overlapping parts of the first and second picture electrodes, an electro-optic material between the first and second substrates and a color filter present on the first substrate, wherein viewed transversely to the first substrate, within a pixel, the color filter partly covers the reflecting part of the first picture electrode. By such a configuration, light from an uncovered part of a picture electrode is mixed with light from the part of the electrode that is covered by the color filter to increase the intensity of the display.

Abstract: A side-emission type semiconductor light-emitting device 10 includes a substrate 12, and the substrate 12 is provided with a case 14 formed of a resin having opacity and reflectivity. The substrate 12 is formed, on its surface, with electrodes 18a and 18b onto which an LED chip 20 is bonded. A transparent or translucent resin 16 is charged between the substrate 12 and the case 14 whereby the LED chip 20 is molded. A light-emitting surface of the side-emission type semiconductor light-emitting device 10 includes surfaces 16a, 16b and a surface opposite to the surface 16b which are formed of the transparent or translucent resin 16. Furthermore, the light-emitting surface is formed by a roughened surface. Due to this, a light outputted from the LED chip and a light reflected from the case 14 is scattered by the light-emitting surface.

Abstract: Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word lines. The spacers are subsequently covered together with the word lines with a nitride layer. Borophosporosilicate glass is introduced between those portions of the nitride layer which respectively belong to a word line and is removed selectively with respect to the nitride using a mask. Contact hole fillings for the electrical connection of the buried bit lines are introduced into the contact holes thus formed.

Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

Abstract: A customizable integrated circuit including a substrate, a plurality of logic units formed on the substrate and a plurality of metal routing layers formed on the substrate for interconnecting the plurality of logic units. The plurality of metal routing layers includes a first routing layer including a plurality of elongate conductors extending generally in a given direction, a second routing layer including a plurality of transversely extending conductors, each adapted for interconnecting a termination of one of the plurality of elongate conductors to a beginning of another one of the plurality of elongate conductors and at least a third routing layer, including a plurality of local routing conductors, a plurality of customizable connections between pairs of the plurality of elongate conductors via individual ones of the plurality of transversely extending conductors and customizable connections between individual elongate conductors and a plurality of individual local routing conductors.

Abstract: A vertical power component on a silicon wafer, including a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and an isolating wall formed by etching a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.

Abstract: The invention relates to methods of making monodisperse nanocrystals comprising the steps of reducing a copper salt with a reducing agent, providing a passivating agent comprising a nitrogen and/or an oxygen donating moitey and isolating the copper nanocrystals. Moreover, the invention relates to methods for making a copper film comprising the steps of applying a solvent comprising copper nanocrystals onto a substrate and heating the substrate to form a film of continuous bulk copper from said nanocrystals. Finally, the invention also relates to methods for filling a feature on a substrate with copper comprising the steps of applying a solvent comprising copper nanocrystals onto the featured substrate and heating the substrate to fill the feature by forming continuous bulk copper in the feature.