Abstract: Embodiments include a semiconductor device and a method for manufacturing the same, which simplify the manufacturing steps and provide split gate type non-volatile memory transistors and other device elements mounted on the same chip. In one method, the step of forming the lower electrode of a capacitor 540 and the step of forming a floating gate 40 of a memory transistor 400 are conducted in different steps. As a result, characteristics of the floating gate 40 and characteristics of the lower electrode 54 can be independently optimized. On the other hand, the step of forming a control gate 36 of the memory transistor 400 and the step of forming an upper electrode 58 of the capacitor 540 are conducted in the same step. As a result, the manufacturing process is simplified.

Abstract: There is provided a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy. In order to solve the above problem, the manufacturing method includes a step of removing a resist mask after a step of implanting an ion of a rare gas element. Also, another manufacturing method includes a first step of implanting an ion of an impurity element for imparting a conductivity type, a second step of implanting an ion of a rare gas element, and a third step of removing a resist mask after the first step and the second step.

Abstract: Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.

Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Abstract: A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

Abstract: A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

Abstract: Included in the invention are laminates having layers of group III-V materials having low dislocation densities, semiconductor devices fabricated using low dislocation density group III-V layers, and methods for making these structures. Some of the inventions are concerned with GaN layers, GaN semiconductor devices, and semiconductor lasers fabricated from GaN materials. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a disposable gate on a semiconductor substrate in a region where a gate electrode is to be formed, forming a sidewall spacer on a sidewall of the disposable gate, forming a source and drain in the semiconductor substrate using the disposable gate and the sidewall spacer as a mask, forming an interlevel insulating film on the semiconductor substrate so as to cover the disposable gate, planarizing an upper surface of the interlevel insulating film to expose upper surfaces of the disposable gate and the sidewall spacer, removing the disposable gate to form a trench portion having a side surface formed from the sidewall spacer and a bottom surface formed from the semiconductor substrate, depositing a gate insulating film on the semiconductor substrate so as to cover the bottom surface and side surface of the trench portion, forming a gate electrode buried in the trench portion, and removing the sidewall spacer and the gate insulating

Abstract: Elements in a triple-well MOS transistor are prevented from being destroyed due to an increase in current consumption or a thermal runaway of a parasitic bipolar transistor. A triple-well NMOS transistor comprising a P well area formed within an N well area and a MOSFET formed in the P well area, an impurity-diffused area having a lower impurity concentration than an N+ drain area is formed close to the N+ drain area, thereby restraining substrate current. The impurity concentration of the P well area is increased to reduce the current gain of a parasitic bipolar transistor. To further reduce the current gain, a punch-through stopper area may be formed. The impurity concentration of the impurity-diffused area is set to equal that of an N− LDD area 31 of a fine CMOS device integrated on the same substrate 1. These areas are formed during a single ion injection step.

Abstract: The present invention is characterized in that gettering is performed such that impurity regions to which a noble gas element is added are formed in a semiconductor film and the metallic element included in the semiconductor film is segregated into the impurity regions by laser annealing. Also, a reflector is provided under a substrate on which a semiconductor film is formed. When laser light transmitted through the semiconductor film substrate is irradiated from the front side of the substrate, the laser beam is reflected by the reflector and thus the laser light can be irradiated to the semiconductor film from the read side thereof. Laser light can be also irradiated to low concentration impurity regions overlapped with a portion the gate electrode. Thus, an effective energy density in the semiconductor film is increased to thereby effect recovery of crystallinity and activation of the impurity element.

Abstract: An electronic chip formed of at least one second elementary chip set in first elementary chip so that the surfaces of the elementary chips are substantially in the same plane wherein the first elementary chip is formed of a heterogeneous substrate including a surface layer above a layer of different doping and defining at least one cavity extending the entire thickness of the second layer and at least one metal interconnection level connecting the at least one second elementary chip to the first elementary chip.

Abstract: A device having a semiconductor component and a printed circuit board are described. The semiconductor component has external contacts and the printed circuit board has contact terminals. The contact terminals display a central blind opening, into which the external contacts of the semiconductor component protrude and are in a force-locking engagement with the contact terminal areas. In the method of electromechanically connecting the two parts to form a device, after they have been aligned, the two components are merely pressed onto each other.

Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.