Abstract: A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls an activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor; and activating a low level language microcode program or hardware logic circuit for performing the called activity if the sensing step detects the second type depictor.

Abstract: The reconfigurable pipelined processor includes a plurality of memory devices and arithmetic units interconnected by cross bars for transferring raw and processed data therebetween. A counter is connected with the cross bar to provide a source of addresses for the memory devices. At least one variable tick delay device is connected with each memory and arithmetic unit to variably control the input and output operations thereof to selectively delay the memory devices and arithmetic units to align the data for processing in a selected sequence.

Abstract: In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs).

Abstract: A method for transferring idempotent and non-idempotent requests (repeatable and non-repeatable requests respectively) over a network between two or more computer systems. The method includes sending a series of messages over a network to perform the request. The method defines several types of messages: a request message, a response message, a slow request message, and an acknowledge message. A slow request is handled by sending a slow request message in response to a retransmitted request message. When the computer system which received the request message has completed the request, a response message is sent to the requesting computer system. The requesting computer system then transmits an acknowledge message to acknowledge receipt of the response if the requesting computer system has received a slow request message even if the request was idempotent. The method reduces the amount of request message traffic on a network of the type where messages are subject to loss.

Abstract: A memory control method and apparatus useful in an input/output buffer memory of a multistation system. The buffer memory storage locations are dynamically divided into a plurality of unit groups having varying storage capacities, and flags are provided which indicate whether or not units are in use. When buffer memory is requested, the size of the requested area is divided by the size of a unit to determine the number of units required and a bit pattern indicating this number is provided. The bit pattern is successively compared and shifted with respect to the flags until the required number of adjacent unused units is found.

Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure which includes an instruction pipeline and an execution pipeline. Each of the instruction and execution pipelines has a plurality of serially operating stages. The instruction pipeline reads instructions from storage and forms therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. A program instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction.

Abstract: A method for pitch-aligned high frequency regeneration of a speech signal which has been sampled at a known sampling frequency f.sub.S and decimated at a known integer decimation ratio N practiced in the receiver portion of a RELP vocoder includes the steps of: providing at least one local carrier signal(s), (each) at a frequency which is an exact integer multiple of a baseband pitch estimate frequency recovered from received data; amplitude modulating each of the local carrier signals with baseband residual data recovered in the receiver portion to provide partial spectrum data; removing, only if the decimation ratio is even, the lower sideband data from the lowest frequency local carrier signal to obtain partial spectrum data; and adding the residual baseband data to the partial spectrum data to obtain PA-HFRed output data from which to reconstruct the speech signal.

Abstract: An arrangement to couple at least one I/O device to the main bus between a CPU and a main memory in a digital computer system is shown to include a random access memory made up of a dedicated part of the main memory and control circuitry to allow access between addresses in the random access memory and either the CPU or the at least one I/O device, such circuitry being arranged to give priority of access to the CPU except when data is actually being transferred from the I/O device and the random access memory.

Abstract: A data processing system has a working or buffer store connected between a main or bulk store and a vector processing unit. The buffer store contains one or more vitual vector registers operable under user control in register-to-register vector operations. A user instruction specifies the length of a vector operand to be processed, the type of operation to be performed, and which vector registers will be used. Vector processing is controlled by a series of programs defined at the code level of the processing unit where for a given function or operation, the same program is used for both register-to-register and storage-to-storage processing. The latter processing is controlled by passing predetermined parameters to the program whereas register-to-register processing is controlled by passing parameters generated in response to user program instructions.

Abstract: A processor system having one or more stations (22, 24, 26) which are interconnected by a general communication network (20). Each station has one or more processors (34, 36). Superprocesses (74, 76, 78) which have one or more processes (80-90) can be executed in the stations. Each superprocess is provided with mail-box space (50, 52, 54) for communication with the environment, in which mail-box space the relevant superprocess and other superprocesses can write but in which only the relevant superprocess itself can read. Processes within the same superprocess have variable data in common, but their register stacks are private. Each mail-box is provided with a filling indicator. In the case of a read operation in an empty mail-box space, a wait signal is issued for the initiating process; write operations in a full mail-box space produce an error signal. There is also provided a job control system for allocating jobs among the stations by way of an application load file.

Abstract: An intelligent input/output system for a programmable controller includes a plurality of input/output (I/O) modules, each of which may be located in proximity to the process being controlled. Each module is interconnected, via a communications link, to a central processor unit (CPU) through an I/O controller. Each module is made up of a plurality of input/output circuits and each may be selectively operated as an input circuit or as an output circuit. The selection is preferably under control of the CPU. Each I/O module includes an operations control unit for controlling each I/O circuit and for providing an exchange of diagnostic and control signals between each I/O circuit and the I/O controller and CPU. Communications between the operations control unit and each I/O circuit is preferably carried out via a pair of conductors, one conductor of which conveys a set of recurring control signals (e.g., in signal frames) and the other of which conveys encoded diagnostic signals.

Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure including an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The stages read from and modify memory at various stages of instruction processing. Collisions between data read from a register in the instruction pipeline phase of operation in response to a first instruction and write data written into the register during the execution phase of operation in response to an earlier instruction can be detected and predicted. In response thereto, the new data can be substituted directly for the modified data in the pipeline itself to provide continued valid operation. In addition, the apparatus and method provide for altering the flow of the instructions through the pipeline in order to accommodate newly generated data and to avoid invalid operation.

Abstract: A pointer, N, indicates an address in a virtual memory space of a demand paged memory including a plurality of virtual address pages and a fixed number of physical memory pages into which blocks of information can be written. A back-up memory store is provided for containing paged-out memory pages. The pointer, N, is advanced along the virtual address pages to indicate the next available virtual address page for allocation, and newly allocated blocks are located on the virtual address page pointed to by said pointer N. Should the necessary space for a block allocation not exist on the page pointed to by said pointer, N, a page which is most recently used and least sparsely utilized is identified from the physical pages onto which blocks have been previously written the block is allocated on that page. If no space remains on the virtual address pages in physical memory for block allocation, then, a least recently used and most sparsely allocated page is identified and paged-out to the back-up store.

Abstract: A memory bus architecture uses a standard unified bus, microprocessor system, and separate memory bus. Access to memory banks coupled to the memory bus may be made by subsystems communicating over the unified bus using the standard protocol of the unified bus, or may be made by the microprocessor using an access protocol method wherein an accessed memory bank generates an acknowledgement signal upon receipt of a READ or WRITE command rather than after the completion of the respective READ or WRITE operation. A further aspect is an Early READ/WRITE circuit that rapidly detects the initiation of a READ or WRITE command by the microprocessor by decoding standard microprocessor status signals in order to generally commence a READ or WRITE operation prior to the time that a normal READ or WRITE operation would be commenced.

Abstract: Apparatus and methods for retrieving bipolar, standardized, digital communication words for test purposes from a source transmitting over a system bus, and displaying these communication words in an understandable format. The apparatus incluldes signal receiving ports coupled to the desired bus, which monitor and retrieve preselected communication words that are transmitted to one or more line replaceable units connected to that bus. Each incoming communication word contains an encoded label which is repetitively compared to a preselected label so that only those communication words having matched labels are retrieved for display. The retrieved word is decoded in either engineering or binary form and then displayed at an LCD window, printed out as hard copy, or made available to an IEEE-488 interface.

Abstract: A single-chip microprogrammable sequence controller includes a subroutine stack and conditional branching facilities. The controller performs a test and mask operation followed by comparison with a user-defined constant to effect a Boolean sum-of-product function. Address control logic includes a flag signal set by compare logic; the flag is available to a microinstruction decoder where it can be used during a subsequent conditional branch operation based on the setting of the flag.

Abstract: In a word processing system, a text stream is stored on a direct access storage device (DASD) for recall and editing. The text stream is organized into a document that is stored on the DASD as a data set. The data set comprises an index portion and a portion containing text records. The index portion is divided into nodes, of which the primary node is called the root node. A method called shadowing is introduced to protect index nodes from the loss of significant data. Status indicators are defined and maintained so that access to a data set for normal system operation may be prevented where there is significant chance that the data set index has errors or is inconsistent to the extent that the normal high performance access method routines may not be able to use the index or may cause inadvertent loss of valid text data.

Abstract: A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory.

Abstract: A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjuction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents.

Abstract: A floppy disk drive controller interface implemented as an integrated circuit on a single semi-conductor chip. The controller connects to a host computer data bus and one or more floppy disk drives. Based upon clocking and control signals received from a digital computer, the controller generates serial encoded data for recording on a floppy disk and receives serial encoded data previously recorded on a floppy disk. The controller comprises a read control circuit including a read data register, write control means including a write data register, a mode register, a status register, state latches, a decoder and special function registers. The controller operates by the setting and clearing of the state latches and reading or writing the mode register, the status register, the special function registers, the read data register and the write data register. The setting of a state latch and accessing of a register is done simultaneously.