Patents Examined by C. H. Lynt
  • Patent number: 4739471
    Abstract: A basic instruction for moving a string of bytes in a word has been devised. Because the operations in the instruction are basic, very few variations are necessary to accommodate diversity of lengths and variables. These operations are imbedded in a single code sequence; the compiler can therefore generate exactly the minimum sequence necessary to perform the operations and can precompute many of the operands at compile time, typically completing the instruction within a single cycle time. The control necessary to optimize the operations is then in the compiler instead of the hardware.
    Type: Grant
    Filed: June 28, 1985
    Date of Patent: April 19, 1988
    Assignee: Hewlett-Packard Company
    Inventors: Allen J. Baum, William R. Bryg
  • Patent number: 4739477
    Abstract: An application composite editor for compound documents containing not only text but also graphics and tables to facilitate the manipulation of object sets in the formatting algorithm. The editor works with a page layout philosphy wherein data objects reside on the page and data resides in the data objects. All pages reside within a document object, and some data objects may have additional objects within them. Objects are data-specific entities that the user can manipulate on the page. All objects exist within a specified boundary on the page, and this boundary is defined as an object set boundary. Object sets may be moved into positions on the page such that more than one object set is occupying a single displayable area on the page. Such an arrangement of objects creates a structure called a superblock. A superblock is any displayable area containing two or more objects sets positioned so that the object sets overlap one another, reside side-by-side or extend above or below one another.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: April 19, 1988
    Assignee: International Business Machines Corp.
    Inventors: Barbara A. Barker, Irene H. Hernandez
  • Patent number: 4723209
    Abstract: Improvements in an application composite editor for compound documents containing not only text but also graphics and tables facilitate the manipulation of object sets in the formatting algorithm. The editor works with a page layout philosophy wherein data objects reside on the page and data resides in the data objects. All pages reside within a document object, and some data objects may have additional objects within them. Objects are data-specific entities that the user can manipulate on the page. All objects exist within a specified boundary on the page, and this boundary is defined as an object set boundary. Object sets may be moved into positions on the page such that more than one object set is occupying a single displayable area on the page. Such an arrangement of objects creates a structure called a superblock. A superblock is any displayable area containing two or more object sets positioned so that the objects sets overlap one another, reside side-by-side or extend above or below one another.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: February 2, 1988
    Assignee: International Business Machines Corp.
    Inventors: Irene H. Hernandez, Barbara A. Barker, Beverly H. Machart
  • Patent number: 4723211
    Abstract: Improvements in an application composite eidtor for compound documents containing not only text but also graphics and tables facilitate the manipulation of object sets in the formatting algorithm. The editor works with a page layout philosophy wherein data objects reside on the page and data resides in the data objects. All pages reside within a document object, and some data objects may have additional objects within them. Objects are data-specific entities that the user can manipulate on the page. All objects exist within a specified boundary on the page, and this boundary is defined as an object set boundary. Object sets may be moved into positions on the page such that more than one object set is occupying a single displayable are on the page. Such an arrangement of objects creates a structure called a superblock. A superblock is any displayable area containing two or more object sets positioned so that the object sets overlap one another, reside side-by-side or extend above or below one another.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: February 2, 1988
    Assignee: International Business Machines Corp.
    Inventors: Barbara A. Barker, Irene H. Hernandez, Rex A. McCaskill
  • Patent number: 4723210
    Abstract: Improvements in an application composite editor for compound documents containing not only text but also graphics and tables facilitate the manipulation of object sets in the formatting algorithm. The editor works with a page layout philosophy wherein data objects reside on the page and data resides in the data objects. All pages reside within a document object, and some data objects may have additional objects within them. Objects are data-specific entities that the user can manipulate on the page. All objects exist within a specified boundary on the page, and this boundary is defined as an object set boundary. Object sets may be moved into positions on the page such that more than one object set is occupying a single displayable area on the page. Such an arrangement of objects creates a structure called a superblock. A superblock is any displayable area containing two or more object sets positioned so that the object sets overlap one another, reside side-by-side or extend above or below one another.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: February 2, 1988
    Assignee: International Business Machines Corp.
    Inventors: Barbara A. Barker, Rex A. McCaskill
  • Patent number: 4720784
    Abstract: A multicomputer network that includes a plurality of individual computers and an interconnection system for interconnecting the computers. An interface is provided for connecting the computers to the network interconnection system which includes a bus controller and a bus.
    Type: Grant
    Filed: October 18, 1983
    Date of Patent: January 19, 1988
    Inventors: Thiruvengadam Radhakrishnan, Clifford P. Grossner
  • Patent number: 4716586
    Abstract: The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware.
    Type: Grant
    Filed: October 17, 1986
    Date of Patent: December 29, 1987
    Assignee: American Microsystems, Inc.
    Inventor: Jerry R. Bauer
  • Patent number: 4710893
    Abstract: A high speed bus structure and data transfer method to provide data transfer capability between a central processing device and a plurality of electrical modules coupled to the bus. In the preferred embodiment, a central processing unit is coupled to a plurality of electrical modules for data reception and transmission. In a module "listen" cycle, the central processor (CP) device generates a function code which is transmitted on a command bus coupled to each electrical module. The CP device asserts data required by the particular module function on the data bus coupled to each electrical module. The CP device transmits an enable signal (ES) on an enable bus to enable the particular electrical module which is to receive data and asserts a clock signal on a clock line coupled to each module. The enabled electrical module receives valid data from the CP device upon sensing a deasserted clock line denoting the end of a clock cycle.
    Type: Grant
    Filed: June 22, 1984
    Date of Patent: December 1, 1987
    Assignee: Autek Systems Corporation
    Inventors: Samuel McCutcheon, Jeffrey Lum, Roman Solek, Troy Harrell, Robert Leman
  • Patent number: 4701844
    Abstract: A pipelined digital computer processor system (10, FIG. 1) is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, FIG. 3) for storing frequently accessed data, and a tag store (82, 92, FIG. 3) for indicating which main memory locations are contained in the respective cache.The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache permitting the use of self-modifying code. The IPU does not write to either cache.
    Type: Grant
    Filed: October 16, 1986
    Date of Patent: October 20, 1987
    Assignee: Motorola Computer Systems, Inc.
    Inventors: Richard F. Thompson, Daniel J. Disney, Swee-meng Quek, Eric C. Westerfeld
  • Patent number: 4683551
    Abstract: Random access memory (RAM) clock switching circuitry for a laser printer having a RAM for storage of microprocessor information plus storage of font information with separate clock generators is provided for use in accessing the two types of information. The switching circuitry has a switch portion for alternately connecting the clock generators to a lockout circuit portion. A lockout request signal from the laser printer microprocessor determines when clock pulses presented to the lockout circuit can be applied to the RAM.
    Type: Grant
    Filed: March 28, 1984
    Date of Patent: July 28, 1987
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: David J. Schoon
  • Patent number: 4660130
    Abstract: A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are "paged-out" to it.
    Type: Grant
    Filed: July 24, 1984
    Date of Patent: April 21, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: David H. Bartley, Timothy J. McEntee, Donald W. Oxley, Satish M. Thatte
  • Patent number: 4654777
    Abstract: An address translation system is provided which has a real storage, a virtual storage having a "V.dbd.R" segment (first segment), second segments to be subjected to two-level paging, and page table segments (third segments) to be used as a page table corresponding to the second segments, a segment table, a first page table which corresponds to the second segments, a second page table which corresponds to the page table segments, and a memory control unit having a virtual address register and a microprocessor for translating the virtual address in the virtual address register into a real address.
    Type: Grant
    Filed: May 18, 1983
    Date of Patent: March 31, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hiroshi Nakamura
  • Patent number: 4653022
    Abstract: A portable electrocardiogram storing apparatus has an electrocardiogram amplifier, an A/D converter for sampling the amplifier output and converting it into a digital signal, a patient actuatable switch, a plurality of electrocardiogram memories, and means for selecting one of the memories for storing the digital signal when the switch is actuated. A time memory is also provided for storing a time when the apparatus is set, and a timer measures a lapse time after the setting. A selected electrocardiogram memory also stores the content of the timer at the time a respective digital signal is stored therein.
    Type: Grant
    Filed: September 21, 1984
    Date of Patent: March 24, 1987
    Assignee: Kabushiki Kaisha Tatebe Seishudo
    Inventor: Tsuneo Koro
  • Patent number: 4653021
    Abstract: A data management apparatus includes a scanner for reading a plurality of pieces of image information, an optical disk for storing a plurality of pieces of image information read by the scanner, a keyboard for entering attribute names featuring the respective pieces of image information stored in the optical disk, a magnetic disk for storing classification names having higher correlation with the attribute names, and a display. The attribute name entered at the keyboard is used as a parameter to access the magnetic disk to retrieve the classification name having the highest similarity. This classification name is displayed on the display.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: March 24, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shiro Takagi
  • Patent number: 4641276
    Abstract: Serial data transfer circuitry is provided for transferring data between a multiplicity of functional units of a VLSI semiconductor chip. Each functional unit is provided with a respective data register, the registers being adapted to receive information in parallel from and/or transfer information in parallel to their respective functional units. The registers are each serially connected in a closed loop for serially shifting data from one register to another. Data transfer from one functional unit to another is accomplished by transferring a data word in parallel to a source register from its respective functional unit, serially shifting data from the source register to a destination register and parallelly transferring the data word from the destination register to its respective functional unit. Control of the transfer is provided by a counter which counts the number of shifts required to transfer the data word from the source to the destination register.
    Type: Grant
    Filed: October 22, 1984
    Date of Patent: February 3, 1987
    Assignee: General Electric Company
    Inventor: Robert J. Dunki-Jacobs
  • Patent number: 4639863
    Abstract: A self contained fixed rotating disk expansion board subsystem may be installed and connected at an expansion slot location of a host computer. The subsystem includes an enclosed head/disk assembly, and circuit elements mounted on a printed circuit board which includes a connector for connecting to the control, data and address buses of the host computer at the expansion slot location. The head/disk assembly is mounted to a mounting substrate which may be the circuit board or which may be a frame to which the circuit board is also attached. Input/output routines are preferably provided to enable the host computer to make use of the subsystem without software driver modifications in the host operating system.
    Type: Grant
    Filed: June 4, 1985
    Date of Patent: January 27, 1987
    Assignee: Plus Development Corporation
    Inventors: Joel N. Harrison, William G. Moon, Randolph H. Graham
  • Patent number: 4638452
    Abstract: A programmable controller includes a main processor which executes a user control program. The main processor is interrupted by a support processor which operates as a real time clock. The interval between interrupts is determined by instructions within the user control program and may be dynamically altered when required. The main processor executes a user created interrupt routine when each interrupt occurs.
    Type: Grant
    Filed: February 27, 1984
    Date of Patent: January 20, 1987
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Ronald E. Schultz, Otomar Schmidt, David A. Johnston
  • Patent number: 4630192
    Abstract: In a computer system, an instruction is executed. The results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. This information is used by the computer system during the execution of subsequent instructions. The results of the execution of the instruction comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction.
    Type: Grant
    Filed: May 18, 1983
    Date of Patent: December 16, 1986
    Assignee: International Business Machines Corporation
    Inventors: Edward R. Wassel, Gerald J. Watkins