Abstract: A method, system and computer program product for detecting when insufficient RAM is available in a computer system, and estimating the additional RAM needed to avoid excess paging. The invention uses memory management parameters to estimate the number of frequently-used pages stored in “virtual memory” on disk. If this estimate is nonzero for an appreciable period the amount of RAM is insufficient, and RAM equal to the estimate should be added to the system.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

Abstract: A microcomputer comprises a CPU, a built-in memory and a memory controller. The memory controller performs access control to the built-in memory in response to a memory access request from the CPU. The microcomputer further comprises a wait count register for storing a waiting period relating to memory access. The memory controller reads the waiting period upon receipt of the memory access request, and then, performs the access control to the built-in memory after a lapse of the waiting period. Low power consumption is achieved by utilizing the access control to the built-in memory without controlling a power source and an oscillator.

Abstract: A computer system for CPU command conversion or real-time compilation with excellent performance. A part of a memory is operated as a special memory area for CPU command conversion or for real-time compilation. The computer system includes: a CPU; a memory; a memory controller for controlling the memory; a chip set; a ROM; a special memory setting table for setting a memory capacity to be mounted, and a capacity setting value of the special memory area corresponding to the capacity setting value of the special memory area corresponding to the capacity of each memory capacity; and a special memory area setting unit for reading the capacity setting value of the special memory area corresponding to the capacity of all the mounted memories from the special memory setting table at the time of starting, and then setting the special memory area.

Abstract: An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership.

Abstract: A circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.

Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.

Abstract: A load estimator supplies, to a controller, a load condition signal corresponding to the current load condition and the estimated load condition of the system. An operational setting storage unit stores an operational setting requirement of the entire system. When the controller determines that the operational requirement meets the operational setting requirement, and the load condition signal meets a predetermined requirement, it reads out, from a relocation program storage unit, an optimum relocation program in association with location information stored in a data location information storage unit, and controls a data relocation unit in accordance with the read relocation program. During a process for relocating data, the controller monitors a predetermined requirement of the suspension (execution of writing, etc., data to a data storage unit). When the requirement of the suspension is fulfilled, the controller terminates the data relocation process processed by the data relocation unit.

Abstract: A method for enhanced fragment caching. The method can include identifying in at least one of first and second retrieved page fragments a variable object utilized by the fragment upon execution to produce dynamic content. Separate cache entries can be written for the first and second retrieved page fragments where the first and second retrieved page fragments differ in ways other than an evaluation of the variable object. Otherwise, a single cache entry can be written for both the first and second retrieved page fragments where the first and second retrieved page fragments differ only in the evaluation of the variable object.

Abstract: A data management system for storing data in a multiple-level cache arrangement of a database comprises a multi-tier cache memory for initially storing all data in summary form in a secondary cache which may be the database; a processor for receiving requests for data and for moving requested data from the secondary cache to a primary cache, wherein, when subsequent requests for data are received, the primary cache is searched before the secondary cache; and for periodically synchronizing and merging all data in the primary cache back into said secondary cache to refresh said primary cache and remove stale information. The system is particularly useful for managing a telecommunications system call detail summary database in which telephone call details are collected as AMA records after the calls terminate and the AMA records are forwarded to a call detail database for storage in summary form and analysis by an external system, for example, for fraud analysis or billing purposes.

Abstract: A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page table entry has not been asserted. If the accessed bit is not asserted, an electrical circuit causes an accessed bit exception and branches execution to a second software exception handler. The second software exception handler asserts the accessed bit in the page table entry in main memory. The second software exception handler returns control back to the original memory access, causing execution to resume where it had left off prior to the TLB miss exception.

Abstract: A semiconductor device includes an MPU (Micro Processing Unit) section, a DRAM (Dynamic Random Access Memory) section, a plurality of address registers, and a plurality of address delay compensating units. The MPU section is provided on a chip to output a clock signal and an address signal. The DRAM section is provided on the chip to input the clock signal and the address signal. Each of the plurality of address registers latches the address signal in response to the clock signal. Each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range. The address signal transmission delay time indicates a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal.

Abstract: A disk-cloning method and system is provided for cloning computer data from a source disk to a target disk. This disk-cloning method and system can be utilized, for example, in the computer assembly line to clone a preselected set of software programs to the main hard disk of each computer unit, or as a backup to a hard disk. This disk-cloning method and system is characterized in that the source data are read from the source disk and written onto the target disk in a sector-by-sector manner rather than in a file-by-file manner as the prior art. This feature allows the cloning procedure to be more efficiently carried out than the prior art. Moreover, it allows the disk-cloning procedure to be performed without having to make modifications to the existing FDT (File Directory Table) and FAT (File Allocation Table) on the target disk, thus ensuring the system security of the target disk. This disk-cloning method and system is therefore more reliable and efficient to use than the prior art.

Abstract: A proxy cache maintains a copy of multiple resources from various servers in a network. When the proxy cache must generate a validation request for at least one resource at one of the servers, the proxy cache piggybacks one or more additional cache validation requests related to documents presently stored in the cache but originating from or associated with the server in question. Upon receipt of an indication of the freshness or validity of the cached copy of the document, the proxy cache can then make a determination as to whether to request an update of the document.

Abstract: A method and system which will increase the ability of memory controllers to intelligently schedule accesses to system memory. The method and system provide a memory controller and a requested memory operation buffer structured so that at least one source attribute of a requested memory operation can be identified. In one instance, the requested memory operation buffer has queues, associated with data buses, which can be utilized to identify source attributes of requested memory operations. Examples of such queues are an Accelerated Graphics Port Interconnect queue associated with an Accelerated Graphics Port interconnect, a system bus queue associated with a system bus, and a Peripheral Component Interconnect bus queue associated with a Peripheral Component Interconnect bus where the queues can be utilized by a memory controller to identify the specific bus from which a requested memory operation originated.

Abstract: An electronic bridging device for transferring electronic data between a first device attached to a system bus and a peripheral device attached to a peripheral bus using a bridging circuit. The DMA controller comprises a system bus interface circuit for connecting the DMA controller to the system bus, a peripheral bus interface circuit for connecting the DMA controller to the peripheral bus, a data transfer request circuit for receiving data transfer requests from devices attached to the peripheral bus, and a control logic circuit for controlling the operation of DMA data transfer operations. Immediately upon receipt of one or more data transfer requests, the bridging device performs the following operations: requests access to the system bus, concatenates all pending peripheral bus data words into a single transfer, and transfers all pending requests across the bridging circuit.

Abstract: A multiple user data storage, retrieval and distribution system containing a parallel processing computer system that forms a digital information server. The server contains a plurality of parallel processors each connected to a information storage device. The user data is stored in a distributed manner amongst the information storage devices. The distribution system dynamically allocates the users to the system based upon the user's requested operating mode. As such, during successive user service periods, all the users are supplied their requested data. The system also provides error detection and correction for the data requested by the users. Furthermore, additional data can be added to the information storage devices during each service period and select information storage devices can be recalibrated without affecting system operation.

Abstract: A high speed memory system is disclosed. The high speed memory system remembers the active n memory rows for n banks of memory. When a memory access request for a memory address that falls within one of the active memory rows is received, the memory controller immediately responds to the memory access request. When a memory access request for a memory address that does not fall within one of the active memory rows is received, the memory controller immediately precharges and activates the desired memory address. For read operations, the memory controller responds with the data from the requested memory address after the memory has been precharged. For memory write operations, the memory controller forces the processor to halt the memory write request such that the memory controller will prepare itself by, precharging and activating the desired memory row. When the processor reissues the request, the memory controller will be prepared to immediately process the write request.

Abstract: In an integrated circuit in which data can be read out from a memory (107) by supplying control data through an access port (101), this integrated circuit includes an access detecting circuit (111) for detecting an access using the access port (101) and an output inhibit circuit (120) for inhibiting the output of data from the memory (107) when this access detecting circuit 111 detects the access. Therefore, in the integrated circuit in which data can be read out from the memory (107) outside of the integrated circuit by a standardized protocol, the reading of data that should be made unintelligible can be limited.