Abstract: A method of and apparatus for capturing and processing Continuous media-based data streams transmitted over an IEEE 1394 serial bus manages the use of both receive buffers and process buffers in order to minimize the amount of captured data that is discarded due to unavailable process buffers. When receiving a stream of continuous data. the data is captured and stored within a current receive buffer. When the current receive buffer is full. the captured data within the receive buffer is then read out, processed and stored within a process buffer, if a process buffer is available on a cached list of process buffers. When Full of processed data, the process buffer is then transferred to an application for utilization or further processing of the processed data. If the process buffer is not completely filled, then the process buffer is added back to the cached list of process buffers.

Abstract: A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests.

Abstract: An information record/reproduction device, method and supply medium thereof to speedily acquire information as well as prevent illegal copying. In the recording system of information record/reproduction device, encoded information recorded on a semiconductor memory is read out from an information provider device by an encoder/decoder section and decoded by utilizing an encoder key K[BA] and then output to an encoder section. In the encoder section, the information decoded by the encoder/decoder section is encrypted and output to a RAM device. The encrypted information input into the RAM is then recorded on an magneto-optic disk.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory.

Abstract: In order to make it possible to control titles separately or continuously, title_playback_mode_flag is recorded on an optical disk. When this flag is “1,” the CPU of a system controller, when the reproduction of one title on the optical disk has ended, continues to have the next title reproduced. When this flag is “0,” the CPU, when the reproduction of one title has ended, causes reproduction to be discontinued then.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A memory map for a computer system is configurable. For example a first section of the memory map (e.g., the lower address space) is configurable so that when the process accesses this section, different devices will respond depending on the memory map in effect. In one embodiment, external non-volatile memory is accessed during a first time period based on a reset memory map. After initialization, the memory may is changed to a normal one so that subsequent accesses to the same section of the memory map result in accesses to faster memory (e.g., internal SRAM). In the case where the reset vector and interrupt vectors have relatively close addresses, the configurability of the memory map allows the reset vector to be handled through accesses to non-volatile memory while interrupt vectors are handled through accesses to faster internal SRAM.

Abstract: An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.

Abstract: The effect of Single Event Upsets (SEUs) occurring in cache memory (103) utilized in satellites is reduced. The idle time of a processor (102), utilizing cache memory (103), is monitored. If processor (102) idle time reaches a predetermined minimum (205), cache memory (103) is engage. When processor (102) idle time subsequently reaches a predetermined maximum threshold (203), cache memory (103) is disabled.

Abstract: A non-volatile storage subsystem comprises a media I/O controller, a media access channel, and movable storage media. A non-volatile disk storage subsystem bas a read channel coupling a disk controller to a disk head assembly. A read channel interfacing subsystem is provided as part of the storage subsystem, and the read channel interfacing subsystem interfaces a disk controller to the read channel. The read channel interfacing subsystem comprises a set of process units and a pipeline manager.

Abstract: A computer system employs a distributed set of links between processing nodes (each processing node including at least one processor). Each link includes a clock signal which is transmitted with and in the same direction as the signals carrying information on the link. The line carrying the clock signal may be matched to the information lines, controlling skew and transport time differences to allow for high frequency operation. Because the clock signals at a transmitter and a receiver may not have a common source, a receive buffer may be employed. Data transmitted across the link is stored into the receive buffer responsive to the transmitter clock signal (e.g. by maintaining a load pointer controlled according to the transmitter clock), and is removed from the buffer responsive to the receiver clock signal (e.g. by maintaining an unload pointer controlled according to the receiver clock). The buffer includes sufficient entries for data to account for clock uncertainties (e.g. skew and jitter).

Abstract: A non-volatile memory installed inside an IC card having a main area and a temporary storage area. The main area is the area in which data is referred to by a host computer. The temporary storage area is the area in which data is transmitted and written by the host computer. Data from the host computer is copied to the main area after being written once in the temporary storage area. Further, data inside the temporary storage area which has not been yet copied is then copied to the main area at the time of power-up. Therefore, even if a power interruption occurs while data is input from the host computer to the IC card, data inside the main area is never destroyed and data inside the main area can be restored based on data remaining in the temporary storage area.

Abstract: A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.

Abstract: A computing device (12) includes a first process (16) and a second process (18) executing thereon in conjunction with a local memory (20). The local memory (20) stores data files retrieved from a database (14). The database (14) maintains the data files in page formats. Each page (22) maintained within the database (14) includes a counter location (24). The first process (16), desiring to write access a particular page (22), increments the counter location (24). The counter location (24) provides an indication that the contents of the particular page (22) are not valid. The second process (18), desiring to read or write access the particular page (22), determines that the particular page (22) is not in a valid state according to the counter location (24). The first process (16), upon terminating write access to the particular page (22), increments the counter location (24). The counter location (24) now provides an indication that the contents of the particular page (22) are in a valid state.

Abstract: The location of large caches of memory located at the network server platform can reduce traffic on the network trunks or Internet backbone. In some instances these memory caches might be located at the facilities management platform. Those users supported on a specific network server platform no longer would be required to download regularly used information from the Internet backbone minimizing congestion on the network. These memory caches can be supplemented or refreshed with new data on a regular basis based on the requirements or changing requirements of the users. The close location of regularly accessed data allows for faster downloads and minimizes congestion on the communication network. In addition to user requested information, push information can be stored in these caches for fast downloading to the users.

Abstract: A set-associative cache-management method combines one-cycle reads and two-cycle pipelined writes. The one-cycle reads involve accessing data from multiple sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. The two-cycle write involves finding a match in a first cycle and performing the write in the second cycle. During the write, the first stage of the write pipeline is available to begin another write operation. Also, the first-stage of the pipeline can be used to begin a two-cycle read operation-which results in a power saving relative to the one-cycle read operation. Due to the pipeline, there is no time penalty involved in the two-cycle read performed after the pipelined write. Also, instead of a wait, a no-op can be executed in the first stage of the write pipeline while the second stage of the pipeline is fulfilling a write request.

Abstract: The memory space (often in the form of cache) in a system (e.g., an Internet proxy or web browser) is conserved by saving low resolution versions of data objects when the full resolution version is removed (e.g., due to age, using a least recently used (LRU) replacement policy) in order to create space for new objects. This provides for efficient use of the memory space. In many situations, the low resolution version of the data object is of adequate quality for usage. Further, even when this is not the case, it can be useful to quickly obtain a low resolution version and then with some delay, obtain the full resolution version at the user or application's request. Particular advantageous embodiments of methods, apparatus and article of manufacture implementing the invention are presented.

Abstract: A network of integrated communication switches and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor computer architecture. The nodes contain multiple processors operatively connected to associated memory units through memory controllers. The communication switches and coherence controllers has associated coherence directories which maintain coherence information for all memory lines that are “homed” in the nodes that are directly connected to the particular communication switch and coherence controller.

Abstract: The operation of a shadow processor for a system having redundant controllers is arranged so that it receives a FIFO fill indicator from another shadow processor associated with that one of the controllers that is in a standby mode, and, if the value of the indicator reaches a predetermined value, then the shadow processor throttles the data writing activity of the active controller for an amount of time sufficient to allow the other shadow processor time to unload the FIFO below a particular fill level.

Abstract: A solid state disk system having an electrically erasable and programmable read only memory is disclosed. The solid state disk system comprises a host interface for inputting data from and outputting data to a host computer located outside of said solid state disk system, a buffer memory coupled to the host interface for temporally storing data, an EEPROM coupled to the buffer memory, a micro-controller coupled to the host interface and buffer memory for controlling a replacement procedure. The EEPROM has a memory region divided into a plurality of blocks each of which is erased at the same time. The memory region has a user block region storing data accessed from the host computer, a spare block region storing data from the outside for replacing any defective block within the user block region, and a replacement information region storing information about an address of a spare block corresponding to the defective block.