Patents Examined by Caleb E Henry
  • Patent number: 11978693
    Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
  • Patent number: 11978760
    Abstract: A display module is disclosed. The display module includes a substrate, a plurality of micro light-emitting diodes (micro-LEDs) disposed on the substrate and configured to radiate light, a reflective layer surrounding a lateral surface of each of the plurality of micro-LEDs, and a light blocking layer disposed on the reflective layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinhyun Cho, Heungbom Kim, Hojin Yu, Wonyong Lee, Hyounggil Choi
  • Patent number: 11974431
    Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Zhiliang Xia
  • Patent number: 11974448
    Abstract: The present disclosure provides a quantum dot light emitting diode, including: a first electrode, a second electrode, a quantum dot light emitting layer between the first electrode and the second electrode, at least one electron transport layer between the quantum dot light emitting layer and the first electrode, and an electron contribution layer between the electron transport layer of the at least one electron transport layer closest to the first electrode and the quantum dot light emitting layer; a material of the electron contribution layer includes a metal material. The embodiment of the present disclosure also provides a method for manufacturing the quantum dot light emitting diode and a display panel.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 30, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jingwen Feng, Yichi Zhang
  • Patent number: 11968892
    Abstract: Provided is an organic light emitting device comprising: an anode; a cathode; a light emitting layer provided between the anode and the cathode; and an organic material layer provided between the cathode and the light emitting layer, wherein the light emitting layer comprises a compound of Chemical Formula 1, and the organic material layer provided between the cathode and the light emitting layer contains a compound of Chemical Formula 2.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 23, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Jungoh Huh, Sung Kil Hong, Miyeon Han, Jae Tak Lee
  • Patent number: 11961794
    Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 16, 2024
    Assignee: Amikor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
  • Patent number: 11963386
    Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang Yeong Song, Won Jong Kim, Yi Su Kim, Jong Woo Kim, Hye In Yang, Woo Suk Jung, Yong Chan Ju, Jae Heung Ha
  • Patent number: 11963375
    Abstract: A light-emitting device includes a first electrode. a second electrode facing the first electrode, and an interlayer between the first electrode and the second electrode and including an emission layer. The emission layer may include a hole transporting host, an electron transporting host, a sensitizer, and a delayed fluorescence dopant. The hole transporting host and the electron transporting host may form an exciplex. The sensitizer may include an organometallic compound. The delayed fluorescence dopant may not include a metal atom, and the exciplex may satisfy specific Equations.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jiyoung Lee, Makoto Yamamoto, Toshiyuki Matsuura, Hyunyoung Kim, Hyosup Shin
  • Patent number: 11955355
    Abstract: A method and apparatus for substrate processing and a cluster tool including a transfer chamber assembly and a plurality of processing assemblies. Processing chamber volumes are sealed from the transfer chamber volume using a support chuck on which a substrate is disposed. A seal ring assembly is coupled to the support chuck. The seal ring assembly includes an inner assembly, an assembly bellows circumscribing the inner assembly, and a bellows disposed between the inner and outer platform. An inner ring is disposed between inner assembly of the seal ring assembly and the bottom surface of the support chuck. An outer ring disposed between the seal ring assembly and the lower sealing surface of the process chamber wall. The support chuck is raised to form an isolation seal between the processing chamber volume and the transfer chamber volume using the bellows, the inner ring, and the outer ring.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 9, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kirankumar Neelasandra Savandaiah, Nitin Bharadwaj Satyavolu, Srinivasa Rao Yedla, Bhaskar Prasad, Thomas Brezoczky
  • Patent number: 11948806
    Abstract: In a method of manufacturing a multi-die semiconductor device, a metal leadframe includes a die pad and electrically-conductive leads arranged around the die pad. First and second semiconductor dice are arranged on the die pad. A laser-activatable material is disposed on the dice and leads, and a set of laser-activated lines is patterned, including a first subset coupling selected bonding pads of the dice to selected leads, a second subset coupling selected bonding pads amongst themselves, and a third subset coupling the lines in the second subset to at least one line in the first subset. A first metallic layer is deposited onto the laser-activated lines to provide first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets by electroplating to provide first and second subsets of electrically-conductive tracks. The electrically-conductive lines in the third subset are selectively removed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 2, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Crema
  • Patent number: 11947231
    Abstract: According to one embodiment, a display device includes a gate line extending in a first direction, first and second source lines crossing the gate line and arranged in the first direction, a first light-shielding layer having first and second openings, and an oxide semiconductor layer crossing the gate line, and in the display device, the first opening and the second opening are arranged in a second direction crossing the first direction between the first source line and the second source line, the gate line is located between the first opening and the second opening, and the oxide semiconductor layer has a first overlapping portion overlapping the first opening.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: April 2, 2024
    Assignee: Japan Display Inc.
    Inventors: Hitoshi Tanaka, Kazuhide Mochizuki
  • Patent number: 11942554
    Abstract: In a transistor that includes an oxide semiconductor, a change in electrical characteristics is suppressed and the reliability is improved. A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Yukinori Shima, Masataka Nakada, Masami Jintyou
  • Patent number: 11943864
    Abstract: A fabrication method for stretchable/conformable electronic and optoelectronic circuits and the resulting circuits. The method may utilize a variety of electronic materials including, but not limited to Silicon, GaAs, InSb, Pb Se, CdTe, organic semiconductors, metal oxide semiconductors and related alloys or hybrid combinations of the aforementioned materials. While a wide range of fabricated electronic/optoelectronic devices, circuits, and systems could be manufactured using the embodied technology, a hemispherical image sensor is an exemplary advantageous optoelectronic device that is enabled by this technology. Other applications include but are not limited to wearable electronics, flexible devices for the internet-of-things, and advanced imaging systems.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: March 26, 2024
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Christopher Kyle Renshaw, Zhao Ma
  • Patent number: 11943957
    Abstract: A display apparatus includes a substrate including a display area including a transmission area and a pixel area, and a peripheral area adjacent to the display area; a display element disposed corresponding to the pixel area, the display element including a pixel electrode, an intermediate layer on the pixel electrode, and an opposite electrode on the intermediate layer; a hydrophobic layer disposed corresponding to the transmission area; and a plurality of fine particles disposed on the hydrophobic layer, the plurality of fine particles and the opposite electrode including a same material.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaeik Kim, Hyejin Gwark, Jungsun Park, Heemin Park, Yongsub Shim, Yeonhwa Lee, Joongu Lee, Jongbeom Hong
  • Patent number: 11942327
    Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Aira Lourdes Villamor
  • Patent number: 11937482
    Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a display device and an anti-reflective layer disposed on the display device. The display device includes a plurality of sub-pixel areas distributed in an array manner. The anti-reflected layer includes a plurality of organic light-transmissive thin films corresponding to the sub-pixel areas. A plurality of inorganic nanoparticles are doped in the organic light-transmissive thin films. The inorganic nanoparticles at a side of the organic light-transmissive thin films away from the display device protrude from a surface of the organic light-transmissive thin films to form a plurality of nano moth-eye structures.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 19, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Wenliang Gong, Wenxu Xianyu
  • Patent number: 11937441
    Abstract: Provided a light emitting device including a reflective layer including a plurality of nanostructures that are periodically two-dimensionally arranged, a planarization layer disposed on the reflective layer, a first electrode disposed on the planarization layer, an organic emission layer disposed on the first electrode, and a second electrode disposed on the organic emission layer, wherein the planarization layer includes a conductive material that is transparent with respect to light emitted by the organic emission layer, and wherein the planarization layer is disposed on upper surfaces of the plurality of nanostructures such that an air gap is provided between adjacent nanostructures of the plurality of nanostructures.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: March 19, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Juncheol Bae, Wonseok Jang, Wonjae Joo, Dongmok Whang
  • Patent number: 11937452
    Abstract: The present disclosure provides a display screen and a display device. The display screen includes a display panel; a bonding layer disposed on the display panel; a shielding layer disposed on the bonding layer; and a cover plate disposed on the shielding layer; wherein the shielding layer or the bonding layer includes a photosensitive material, and a light transmittance of the photosensitive material becomes less than a threshold under ultraviolet light.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: March 19, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Mingjun Zhou
  • Patent number: 11937491
    Abstract: A display device includes a substrate including a display area having first color subpixels and a transparent area inside the display area, an array layer in the display area on the substrate, a first electrode in the first color subpixels on the array layer, a first emission assisting layer on the first electrode, an emitting material layer in the first color subpixels on the first emission assisting layer, a second emission assisting layer on the emitting material layer, a deposition preventing layer in the transparent area on the second emission assisting layer, a second electrode on the second emission assisting layer, the second electrode selectively disposed in a region where the deposition preventing layer is not disposed, an encapsulating layer on the deposition preventing layer and the second electrode, a polarizing layer in the display area on the encapsulating layer, an auxiliary equipment in the transparent area under the substrate.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 19, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Nam Lim, Hyun-Chul Choi, Kwan-Soo Kim, Seok-Hyun Kim, Jae-Hyeon Kim
  • Patent number: 11929311
    Abstract: A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivek K Arora, Woochan Kim