Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure. The TFE structure includes at least one dielectric layer and at least two barrier layers, and the TFE structure is formed over the OLED structure. The at least one dielectric layer is deposited by atomic layer deposition (ALD). Having the at least one dielectric layer formed by ALD in the TFE structure improves the barrier performance of the TFE structure.

Abstract: The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion.

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract: A solid-state imaging device has a first area in which a plurality of pixels are provided, a second area provided on an outer side with respect to the first area, and a third area provided on the outer side with respect to the second area. An inner-lens layer provided over the first to third areas has an opening. An insulating film provided below the inner-lens layer also has an opening.

Abstract: A semiconductor manufacturing method includes preparing a substrate having a metal film formed on a surface thereof; forming an oxide layer by oxidizing a surface of the metal film by plasma of a mixed gas of an oxygen-containing gas and a hydrogen-containing gas; and forming a thin film on the oxide layer by supplying at least an oxidizing gas to the substrate.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Abstract: A thin film transistor, a method of fabricating the same, an array substrate and a display device are disclosed. The method of fabricating the thin film transistor comprises: forming a semiconductor layer; forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer; forming a source electrode and a drain electrode on the protective layer; and removing a portion of the protective layer between the source electrode and the drain electrode to expose a portion of the semiconductor layer between the source electrode and the drain electrode.

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.

Abstract: The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.

Abstract: A method of forming a patterned mask layer includes the following steps. A plurality of support features is formed on a mask layer. A plurality of spacers is formed on side walls of the support features. A patterned protection layer is formed on the support features and top surfaces of the spacers. At least a part of side surfaces of the spacers are not covered by the patterned protection layer, and the patterned protection layer is formed in a process environment containing methane (CH4). A trimming process is then performed to remove a part of each of the spacers. Tapered parts of the spacers may be removed by the trimming process before the step of etching the mask layer with the spacers as a mask, and the critical dimension uniformity of the patterned mask layer may be improved accordingly.

Abstract: A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.

Abstract: A method of preparing two dimension bent X-ray crystal analyzers in strips feature is provided. A crystal wafer in strips is bonded to a curved substrate which offers the desired focus length. A crystal wafer in strips is pressed against the surface of the substrate forming curved shape by anodic bonding or glue bonding. The bonding is permanently formed between crystal wafer and its substrate surface, which makes crystal wafer has same curvature as previously prepared substrate.

Abstract: Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.

Abstract: In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is disposed in the high resistivity substrate. Further, a first well region having the first conductive type is disposed on the deep well region, and the transistor is disposed on the first well region.