Abstract: Circuits which self-destruct under radiation are provided. In one aspect, a method for creating a radiation-sensitive circuit is provided. The method includes the step of: connecting an integrated circuit to a power supply and to a ground in parallel with at least one dosimeter device, wherein the dosimeter device is configured to change from being an insulator to being a conductor under radiation. Radiation-sensitive circuits are also provided.

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

Abstract: An array substrate, a manufacture method thereof, and a liquid crystal display device (LCD) are provided. The array substrate includes a substrate; and a plurality of sub-pixel units disposed on the substrate. The sub-pixel unit comprises a thin film transistor (TFT), a pixel electrode, a common electrode and a passivation layer. The thin film transistor comprises an active layer, a gate electrode, a source electrode and a drain electrode. The drain electrode is electrically connected with the pixel electrode. The passivation layer covers the source electrode, the drain electrode and the pixel electrode. The sub-pixel unit further includes a test electrode which is electrically connected with the pixel electrode and is exposed at an external surface of the sub-pixel unit. With the test electrode, electrical characteristics of the TFT can be tested conveniently, and the quality level of the LCD device can also be improved.

Abstract: A method of manufacturing a mask frame assembly, the method including: forming a first through hole in a vicinity of a first deposition region of a first mask; forming a second through hole in a vicinity of a second deposition region of a second mask; forming a third through hole in a first portion of a supporting stick; forming a fourth through hole in a second portion of the supporting stick; aligning the first through hole with the third through hole; aligning the second through hole with the fourth through hole; inserting a fixing member in the aligned first and third through holes; and inserting the fixing member in the aligned second and fourth through holes, wherein the support stick couples the first mask and the second mask together via the fixing member.

Abstract: A method for forming a device package includes forming a molding compound around a plurality of dies and laminating a polymer layer over the dies. A top surface of the dies is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the dies. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of one of the dies.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

Abstract: Provided is a solder material that has a high melting point and exhibits superior mechanical characteristics, and therefore can form a connecting portion with high heat-resistant reliability.

Abstract: An array substrate includes a plurality of first pixel-unit columns and a plurality of second pixel-unit columns repeatedly alternating with each other along a first direction. The first pixel-unit column includes a plurality of first pixel-unit groups and a plurality of second pixel-unit groups repeatedly alternating with each other along a second direction. The second pixel-unit column includes a plurality of third pixel-unit groups and a plurality of fourth pixel-unit groups repeatedly alternating with each other along the second direction. Each of the first pixel-unit group, the second pixel-unit group, the third pixel-unit group, and the fourth pixel-unit group includes a plurality of sub-pixels arranged into a matrix. The first pixel-unit group and the second pixel-unit group have same quantities of rows and columns in one matrix. The third pixel-unit group and the fourth pixel-unit group have same quantities of rows and columns in one matrix.

Abstract: A method for producing a multilevel microelectronic structure includes formation of a first layer, production of at least one second layer at least partially covering the first layer, and production of at least one microelectronic pattern on or in the second layer. The second layer is formed so as to generate a mechanical stress in it, the first layer forms, for the second layer, a support preventing relaxation of the stress. After the production of at least one microelectronic pattern, the method includes at least elimination of at least part of the first layer, thus making it possible to relax at least part of the mechanical stress on the second layer so that at least a portion of the second layer covering the eliminated part of the first layer moves, and fixing the moved portion of the second layer to a structure part that has remained fixed.

Abstract: In embodiments, a radio frequency (RF) module includes an RF switching device, an RF active device, a passive device and a control device formed on a high resistivity substrate. The passive device can include a shallow trench device isolation region having a plate shape and formed at a surface portion of the high resistivity substrate, deep trench device isolation regions extending downward from a lower surface of the shallow trench device isolation region so as to define at least one isolated region therebetween, at least one insulating layer formed on the high resistivity substrate, and at least one passive component formed on the insulating layer.

Abstract: Dielectric AlO, AlOC, AlON and AlOCN films characterized by a dielectric constant (k) of less than about 10 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers and/or diffusion barriers. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) in an iALD process chamber and the aluminum-containing compound is allowed to adsorb onto the surface of the substrate. This step is performed in an absence of plasma. Next, the unadsorbed aluminum-containing compound is removed from the process chamber, and the substrate is treated with a process gas containing CO2 or N2O, and an inert gas in a plasma to form an AlO, AlOC, or AlON layer. These steps are then repeated.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

Abstract: A method for forming a semiconductor device comprises forming an amorphous or polycrystalline semiconductor layer adjacently to at least one semiconductor doping region having a first conductivity type located in a semiconductor substrate. The method further comprises incorporating dopants into the amorphous or polycrystalline semiconductor layer during or after forming the amorphous or polycrystalline semiconductor layer. The method further comprises annealing the amorphous or polycrystalline semiconductor layer to transform at least a part of the amorphous or polycrystalline semiconductor layer into a substantially monocrystalline semiconductor layer and to form at least one doping region having the second conductivity type in the monocrystalline semiconductor layer, such that a p-n junction is formed between the at least one semiconductor doping region having the first conductivity type and the at least one doping region having the second conductivity type.

Abstract: Provided are a method of forming patterns and a method of manufacturing an integrated circuit device. In the method of forming patterns, a photoresist pattern having a first opening exposing a first region of a target layer is formed. A capping layer is formed at sidewalls of the photoresist pattern defining the first opening. An insoluble region is formed around the first opening by diffusing acid from the capping layer to the inside of the photoresist pattern. A second opening exposing a second region of the target layer is formed by removing a soluble region spaced apart from the first opening, with the insoluble region being interposed therebetween. The target layer is etched using the insoluble region as an etch mask.

Abstract: A method for fabricating an electronic package structure is provided, which includes the steps of: forming a circuit layer on a conductor; disposing an electronic element on the circuit layer; forming an insulating layer on the conductor to encapsulate the electronic element and the circuit layer; and removing portions of the conductor so as to cause the remaining portions of the conductor to constitute a plurality of conductive bumps. As such, when the electronic package structure is disposed on a circuit board through an SMT (Surface Mount Technology) process, the conductive bumps are easily aligned with contacts of the circuit board, thereby effectively improving the yield of the SMT process.

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.