Abstract: A nitride LED having a laminated structure in which a substrate, a n-type cladding layer, an active layer, a p-type cladding layer, and a multi-ohmic contact layer are sequentially stacked, and a manufacturing method thereof, are provided. In the nitride LED, the multi-ohmic contact layer includes multiple layers of a first transparent film layer/silver/second transparent film layer. In the nitride LED and a manufacturing method thereof, ohmic contact characteristics with respect to the p-type cladding layer are enhanced, thereby exhibiting a good current-voltage characteristic. Also, since the transparent electrodes have a high light transmitting property, the light emitting efficiency of the device is increased.

Abstract: A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing member by pressing the pressing member against the flowable film; forming a solidified film having the first concave portion by solidifying the flowable film through annealing at a first temperature with the pressing member pressed against the flowable film; forming a burnt film having the first concave portion by burning the solidified film through annealing at a second temperature higher than the first temperature; forming a second concave portion connected at least to the first concave portion in the burnt film by forming, on the burnt film, a mask having an opening for forming the second concave portion and etching the burnt film by using the mask; and forming a plug and a metal interconnect by filing the first concave portion and the second concav

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region, self-aligned to the narrower, underlying polysilicon layer. Subsequent metallization results in metal coverage, only on the surfaces of the wider polysilicon layer. An anneal cycle then converts only the wider polysilicon feature to a metal silicide, resulting in a polycide gate structure, comprised of a wider, overhanging metal silicide layer, on a narrower, underlying polysiliocn layer.

Abstract: A semiconductor wafer having an SOI (Silicon-On-Insulator) structure and capable of being accurately aligned without undesirable contrast appearing in an infrared transmission image. The wafer is implemented as a laminate SOI wafer including an SOI layer. An aligning oxide film pattern and an oxide film pattern are buried in the SOI layer. The aligning oxide film pattern and oxide film pattern are respectively aligned with an aligning mask pattern and a mask pattern provided on a masking quartz wafer. In this condition, the laminate wafer is subjected to preselected processing. One of opposite major surfaces of the SOI wafer facing the quartz wafer is smoothed over its regions containing at least the aligning oxide film pattern and through which infrared rays are to be transmitted with respect to photoresist. The other major surface is smoothed over the above regions by having a polycrystal silicon film thereof removed.

Abstract: An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the source and drain regions, where the pre-gate regions extend at least partially under the gate electrode. A single heavily doped pre-gate region may be provided for the MOSFET of the electro-static discharge protection circuit.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.

Abstract: A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.

Abstract: The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.

Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.

Abstract: A semiconductor device includes a circuit substrate having a first surface on which a high-frequency circuit is located; a first metal layer disposed on a second surface of the circuit substrate; bump wirings on the first surface of the circuit substrate and electrically connected to the high-frequency circuit; a metal wall disposed on the first surface of the circuit substrate surrounding the high-frequency circuit; a wiring substrate having one surface on which substrate wirings corresponding to the bump wirings are located, the wiring substrate being disposed on the circuit substrate so that the substrate wirings are electrically connected to the bump wirings, and in contact with the metal wall, sealing a region including the high-frequency circuit; and a second metal layer disposed on a second surface of the wiring substrate. An electromagnetic shielding effect sufficient for use in a high-frequency circuit is obtained and fabricating cost is considerably reduced.

Abstract: A Ceramic Bonding Copper (CBC) substrate used in semiconductor modules includes a ceramic plate having foil-shaped copper plates bonded to the ceramic plate by the direct copper bonding method. A circuit pattern is formed on one of the copper plates. The ceramic plate is fabricated by sintering at high temperature an alumina powder compact containing zirconia and one or more of the following additives: yttria, calcia, magnesia, and ceria. The flexural strength and the thermal conductivity of the alumnina ceramic plate of the invention are remarkably improved, facilitating a reduction in the thickness of the ceramic plate. The reduction in thickness of the CBC substrate further improves the ability of the semiconductor device to radiate heat and therefore increases the current carrying capability of the semiconductor device.

Abstract: An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, at least one MDD area, and a heavy concentration source/drain area. Conversely, the PMOS transistor includes an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account, inter alia, the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provides lower source-drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

Abstract: The composite hybrid semiconductor structure contains a support plate substrate (11) with a number of at least two support connector spots (13) and a semiconductor chip or semiconductor wafer substrate (10) with a number of at least two chip connector spots (16). The structures is distinguished by a respectively thermally and electrically conducting adhesive layer (13') on the surface of the support plate substrate (11) within the areas of the support connector spots (13), where the said substrates (10, 11) with the said connector spots (13, 16) placed opposite each other and in electrically conducting and mechanically firm connection have been brought into connection with each other by the said electrically conductive adhesive layers (13').

Abstract: A semiconductor package of the present invention includes a paddle layer having a metal wiring pattern formed therein, semiconductor chips bonded on at least one surface of the paddle layer. A plurality of wires electrically connecting a plurality of chip pads formed on the semiconductor chips with the paddle layer. Each lead includes a first lead bonded to a surface of the paddle layer and a second lead which is at least partially exposed. A conductive adhesive bonds the paddle layer to the first leads and a molding resin comprises the body of the package. The semiconductor package of the above construction has various advantages compared to conventional packages. The occupying area rate can be minimized, and an undesired curving of the lead can be prevented. Further, since the semiconductor chip can be bonded on both surfaces of the paddle layer, an integrated semiconductor package can be achieved.

Abstract: In a lead frame adapted to be used for a semiconductor device, a plurality of inner leads are made of a thin conductive material for easily forming a fine pattern of the inner leads. A plurality of outer leads are integrally formed with the respective inner leads. The outer leads are coated with metal layers to increase the thickness thereof, so that a desired strength of the outer leads is obtained. A semiconductor chip is electrically connected to the inner leads. The semiconductor chip and a part of the lead frame including the inner leads are hermetically sealed with a resin and, thus, a semiconductor device is obtained.

Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: Between an external power supply line and an internal power supply line in which an internal power supply potential is transmitted on a substrate region, a high voltage conducting mechanism is provided, which is rendered conductive when a transitional high voltage surge is generated at the external power supply line by electrically connecting the external power supply line and the internal power supply line. Even when the ground line and external power supply line are not arranged parallel to each other, a high voltage conducting mechanism constituted by a field transistor or an insulated gate type field effect transistor having wide width over a long distance can be formed.