Abstract: A method for manufacturing an electronic component by seal-molding with resin a die pad mounted by an electronic element thereon and loads of input-and-output terminals which are supported by a lead frame having an outer frame and removing such sealed electronic component with mold materials from the outer frame of the lead frame which includes suspending pins for supporting the leads and a first mold holder disconnected from the leads, the method including the steps of resin molding a first mold member on the leads and the first mold holder to join the leads and the first mold member with the first mold member, cutting the suspending pins between the first mold member and the outer frame, resin-molding a second mold member on the first mold member to cover the cut ends of the suspending pins, and cutting the first mold holder between the second mold member and the outer frame to remove thus molded electronic component from the lead frame.

Abstract: An integrated circuit comprises a plurality of interconnected semiconductor devices, at least one the interconnected devices being dielectrically isolated from the substrate, and at least one other of the interconnected devices being junction isolated from the substrate. In a preferred embodiment, at least one of the junction isolated devices comprises an ESD protection circuit. The ESD protection circuit, which preferably includes a zener diode and more preferably further includes a bipolar transistor, a diode, and a resistor, is formed in a trench-isolated island comprising a semiconductor layer of a conductivity type opposite to that of the substrate. A heavily doped buried semiconductor region of the same conductivity type as the substrate is formed in the island semiconductor layer adjacent to the substrate.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.

Abstract: 4-terminal HEMT-HBT composite devices, based upon monolithically integrated HEMT-HBT technology and configured in various topologies, are useful in a wide range of applications which currently utilize discrete MMICs. In particular, the 4-terminal topologies are easily configured as 3-terminal composite devices useful in various 2-port and 3-port MMIC circuit applications, such as low noise-high linearity amplifiers as well as mixers, which provide the benefits of a reduction in size, as well as corresponding cost while providing better performance than utilizing either HEMT or HBT devices individually.

Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.

Abstract: A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes.

Abstract: A semiconductor device includes a flat, square n-type diffusion layer, a p-type channel stopper region, and an electrode. The n-type diffusion layer is formed to be isolated in a check element region of a p-type semiconductor substrate or a p-type well covered with a field oxide film and having circuit element regions and the check element region sandwiched therebetween. The p-type channel stopper region is formed to contact at least one side of the n-type diffusion layer. The electrode is extracted from the n-type diffusion layer through a contact hole. The n-type diffusion layer, the p-type channel stopper region, and the electrode constitute the check element for checking a state of the p-type channel stopper region by measuring a junction breakdown voltage of the n-type diffusion layer.

Abstract: The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.

Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.

Abstract: Pulse shaped voltage of 5V is applied to a source region 3 at initial phase of erase by a pull back voltage generator 13 connected to the sources region 3. Then, the pulse shaped voltages of 10V and 12V increased under stepwise bases are applied to source region 3 with progress of erasion. Generation of hot-holes at the initial phase of data erasion can be prevented because difference in voltage between the floating gate electrode 5 and source region 3 is decreased. Value of the pulse shaped voltage thus applied is increased for the difference occurred between the floating gate electrode 5 and source region 3 when erasion is in much progress. Thus, it is possible to pull out the stored electrons from the floating gate electrode 5 until the threshold voltages can be set at predetermined values. So that, degradation of characteristics of a gate oxidation layer caused by hot-holes generated with erasion can be prevented.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: A superconductive junction (10) comprises a first track (22) of YBa.sub.2 Cu.sub.3 O.sub.7 surmounted by a second track (28) also of YBa.sub.2 Cu.sub.3 O.sub.7. An interconnect (26) in the form of a superconductive mesa electrically connects the first track to the second track and acts as a microbridge. When cooled below a critical temperature, the junction (10) shows Josephson-like behaviour. A non-superconductive layer (24) of PrBa.sub.2 Cu.sub.3 O.sub.7 separates the first track and the second track, with the interconnect extending through the PrBa.sub.2 Cu.sub.3 O.sub.7 layer in the form of an island. The junction (10) is fabricated by electron beam evaporation, optical lithography, and ion beam milling.

Abstract: A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base current of the pnp transistor to a constant level causing operation in the saturation range of the pnp transistor.

Abstract: A micro-switch having a flexible conductive membrane which is moved by an external force, such as pressure from an air flow, to establish a connection between contact pads. The conductive membrane is stretched over one or more spacer pads to introduce deformation in the conductive membrane, thereby improving the accuracy and repeatability of the micro-switch. The spacing between the contact pads and the conductive membrane is precisely controlled by controlling the height difference between the spacer pads and the conductive pads. This height difference is determined by one or more precisely controlled etch operations.

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Abstract: A semiconductor device provide with an ESD circuit including three active regions and element isolating regions formed on a semiconductor substrate in such a manner that the active regions are isolated from one another by the element isolating regions, source/drain diffusion regions respectively formed at the active regions, a first interlayer insulating film formed on the semiconductor substrate in such a manner that it covers the active regions and element isolating regions while being provided with first contact holes for exposing the diffusion regions, first lines formed on the first interlayer insulating film in such a manner that they are electrically connected to the diffusion regions via the first contact holes, respectively, a second interlayer insulating film formed over the entire exposed surface of the resulting structure obtained after the formation of the first line in such a manner that it has second contact holes for exposing the first line disposed over a central one of the active regions, an

Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by bonding of integrated circuit chips into a chip stack and bonding the chip stack onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and across the edge of the chip. Thickness of the metallization feature and bonding material provides a "stand-off" between chips allowing improved heat dissipation by fluid flow, conduction through a viscous thermally conducting material and/or a heat sink disposed between chips in the stack.

Abstract: A semiconductor memory device has memory cells including a capacitor for storing data, and a transistor for inputting a ground voltage at its substrate and for selectively connecting the capacitor to a bit line. The device also has sense amplifiers that sense and amplify data that is transferred from the memory cells to the bit line. The device further has a first internal voltage supply circuit that generates a first internal voltage and supplies it to the sense amplifiers. The device also has a PMOS transistor for switching the first internal voltage from the first internal voltage supply circuit to the sense amplifiers, a second internal voltage supply circuit that generates a second internal voltage and supplies it to the sense amplifiers, and an NMOS transistor for switching the second internal voltage from the second internal voltage supply circuit to the sense amplifiers.

Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.

Abstract: A voltage step-down circuit includes a first transistor having an input terminal supplied with a first power supply voltage, an output terminal and a control terminal. A step-down voltage derived from the first power supply voltage is output through the output terminal when a load circuit to be driven by the voltage step-down circuit is in an active mode. The first transistor is OFF when the load circuit is in a standby mode. A first voltage dividing circuit has an input terminal connected to the output terminal of the first transistor, and an output terminal. A first control circuit controls a voltage of the control terminal of the first transistor so that, when the load circuit is in the active mode, a feedback control is performed on the basis of a result of comparing a reference voltage with a voltage of the output terminal of the first voltage dividing circuit, and so that, when the load circuit is in the standby mode, the feedback control is stopped and the first transistor is OFF.