Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

Abstract: A method of fabricating an organic photovoltaic device. The method includes providing a first electrode which by applying a layer of conductive material onto a transparent substrate. The conductive material forms the first electrode. The method also includes placing an active layer of organic photovoltaic material on top of the first electrode. The active layer is configured to convert photonic energy into electrical energy. Placing an active layer of organic photovoltaic material includes placing an active layer of organic photovoltaic material having ferroelectric dipoles dispersed therein. The method further includes applying a second electrode on top of the active layer of organic photovoltaic material.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Abstract: Systems and methods for calibrating a volume dimensioner are provided. In one embodiment, a calibrating system comprises a dimensioner and a reference object. The dimensioner is configured to remotely sense characteristics of an object and calculate physical dimensions of the object from the sensed characteristics. The reference object has predefined physical dimensions and an outside surface that exhibits a pattern of reference markings. The dimensioner is configured to be calibrated using the reference object as a basis for comparison.

Abstract: A hexagonal single crystal wafer is produced from a hexagonal single crystal ingot. The depth of the focal point of a laser beam is gradually changed from a shallow position not reaching the depth corresponding to the desired thickness of the wafer to a deep position corresponding to the desired thickness of the wafer in such a manner that a parabola is described by the path of the focal point. When the spot area of the laser beam on the upper surface of the ingot becomes a predetermined maximum value, the deep position of the focal point is maintained.

Abstract: Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes providing a substrate having a first and second device wells, a gate dielectric overlying the first and second device wells, a first gate electrode layer overlying the gate dielectric, and a shallow trench isolation structure between the first and second device wells. An insulating dielectric layer is formed only partially overlying the first gate electrode layer. A second gate electrode material is deposited overlying at least the insulating dielectric layer to form a second gate electrode layer. The layers are patterned to form a second gate structure overlying the second device well. A contact is formed on the second gate electrode layer of the second gate structure with the contact overlying dielectric material of at least one of the insulating dielectric layer or the shallow trench isolation structure.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: Provided is a method for manufacturing a composite body, the method containing: a composition preparation process of preparing a composition that contains a polymer having a cationic functional group and having a weight average molecular weight of from 2,000 to 1,000,000, and that has a pH of from 2.0 to 11.0; a composite member preparation process of preparing a composite member that includes a member A and a member B, a surface of the member B having a defined isoelectric point, and that satisfies a relationship: the isoelectric point of a surface of the member B< the pH of the composition<the isoelectric point of a surface of the member A; and an application process of applying the composition to the surface of the member A and the surface of the member B included in the composite member.

Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Abstract: A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Abstract: In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %?(M×C+B)×100/(M+B)?4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

Abstract: In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant asubstrate. The III-nitride layer has a bulk lattice constant alayer. In some embodiments, [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract: A technique includes forming a film containing a first element, a second element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing supplying a first precursor having chemical bonds between the first elements to a substrate, supplying a second precursor having chemical bonds between the first element and carbon without having the chemical bonds between the first elements to the substrate, and supplying a first reactant containing the second element to the substrate.