Abstract: A photovoltaic device includes an intrinsic layer having two or more sublayers. The sublayers are intentionally deposited to include complementary concave and convex shapes. The sum of these layers resulting in a relatively flat surface for deposition of n- or p-doped layers. The photovoltaic device is optionally bifacial.

Abstract: The present disclosure relates to an etchant, a method of making an etchant, an etching method and a method of fabricating a semiconductor device using the same. The etching method includes supplying an etchant on an etch-target layer to etch the etch-target layer in a wet etch manner. The etchant contains a basic compound and a sugar alcohol, and the basic compound contains ammonium hydroxide or tetraalkyl ammonium hydroxide. In the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound.

Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Abstract: Provided is a method of doping a substrate. The method includes providing the substrate, providing a target material on the substrate, and implanting a dopant of the target material into the substrate by providing a laser beam to the target material.

Abstract: A laser annealing apparatus includes: a substrate supporting unit which supports a substrate; a laser beam irradiating unit which irradiates a line laser beam extending in a first direction to an amorphous silicon layer provided on the substrate on the substrate supporting unit; a substrate moving unit which moves the substrate supporting unit in a second direction crossing the first direction; and a first beam cutter and a second beam cutter, which are disposed between the substrate supporting unit and the laser beam irradiating unit, where the first and second beam cutters move to increase or decrease a shielded area of the substrate, which is an area of the substrate overlapping the first or second beam cutter and the line laser beam, to shield from at least a portion of the line laser beam irradiated to a portion of the substrate at an outer portion of the amorphous silicon layer.

Abstract: A method of fabricating an organic photovoltaic device. The method includes providing a first electrode which by applying a layer of conductive material onto a transparent substrate. The conductive material forms the first electrode. The method also includes placing an active layer of organic photovoltaic material on top of the first electrode. The active layer is configured to convert photonic energy into electrical energy. Placing an active layer of organic photovoltaic material includes placing an active layer of organic photovoltaic material having ferroelectric dipoles dispersed therein. The method further includes applying a second electrode on top of the active layer of organic photovoltaic material.

Abstract: A semiconductor device, including a plurality of semiconductor modules, each including a semiconductor element, a main terminal and a wiring portion that connects the semiconductor element and the main terminal, and at least one busbar that each includes a terminal portion, and a plurality of attachment portions, the attachment portions being respectively connected to the main terminals of the semiconductor modules, such that the at least one busbar connects the semiconductor modules in parallel. The largest resistance among all resistances between the terminal portion and each of the attachment portions in each busbar is 10% or less of a resistance of the wiring portion in each semiconductor module. The largest inductance among all inductances between the terminal portion and each of the attachment portions in each busbar is 10% or less of an inductance of the wiring portion in each semiconductor module.

Abstract: According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers, an active layer, a first electrode electrically connected to the first conductive type semiconductor layer, a current blocking layer disposed on a lower surface of the light emitting structure, and a second electrode electrically connected to the second conductive type semiconductor layer. The second electrode includes a first reflective metal layer adjoining the second conductive type semiconductor layer, and a second reflective metal layer covering a lower surface of the current blocking layer and a lower surface of the first reflective metal layer, and adjoining the second conductive type semiconductor layer. A contact resistance between the second reflective metal layer and the second conductive type semiconductor layer is higher than a contact resistance between the first reflective metal layer and the second conductive type semiconductor layer.

Abstract: An OLED display includes pixels, each including a first light emission region having a first area and a first perimeter and a second light emission region disposed neighboring the first light emission region and having a second area and a second perimeter. The first area, the first perimeter, the second area, and the second perimeter respectively satisfy an equation of A1*P2=A2*P1, where A1 is the first area, P1 is the first perimeter, A2 is the second area, and P2 is the second perimeter.

Abstract: A display device includes a first substrate that is provided with a display element in a display region, a second substrate that faces the first substrate, and a sealant that bonds the first substrate and the second substrate to each other in a region surrounding the periphery of the display region in a plan view, in which each of the first substrate and the second substrate has a rectangular shape, in which at least one of the first substrate and the second substrate has a corner portion and a recess formed at a position which is close to the corner portion and overlaps at least a part of the region in which the sealant is disposed, and in which the sealant is provided to be in contact with at least a surface far from the display region among inner surfaces of the recess.

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

Abstract: A motion detection system detects object motion in a medical imaging system. The computer-implemented calibration method includes an automatic calibration process for determining a motion threshold for the object motion detection system, while the object is positioned for imaging by the medical imaging system. The calibration process includes: repeatedly acquiring motion detection data and repeatedly acquiring motion quantification data with a motion quantification system. The motion quantification data are analyzed to determine whether the object was mobile or immobile. If the object was immobile, an object motion threshold for the motion detection system is determined by statistical analysis of the motion detection data.

Abstract: The present technology includes: bonding a device formation side of a first substrate having a first device and a device formation side of a second substrate having a second device in opposition to each other; forming a protective film on at least an edge of the second substrate having the second device; and reducing a thickness of the first substrate.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.

Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Charge is transferred form the detector using a junction field effect transistor (JFET) in each pixel. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.