Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which begins by forming an insulating layer and a passivation layer composed of silicon nitride is over a substrate. A plug contact opening is formed through the passivation layer and the insulating layer. The insulating layer in the plug contact opening is selectively wet etched. The wet etching forms an overhanging portion of the passivation layer. A bottom plug is formed in the contact opening. A first dielectric layer having a cylindrical electrode opening is formed over passivation layer and the plug is exposed. A second polysilicon layer is formed over the first dielectric layer and in the cylindrical openings. A second dielectric layer is formed over the second polysilicon layer and in the cylindrical electrode opening. The second dielectric layer and the second polysilicon layer are planarized.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: An electron beam pumped semiconductor laser includes a semiconductor laser screen and an electron beam source adjacent the semiconductor laser screen. The semiconductor laser screen comprises a transparent single crystal substrate, an electron beam responsive active gain layer on the substrate, and first and second reflective layers. The epitaxial electron beam responsive active gain layer has a crystal structure in alignment with the crystal structure of the substrate, and the first and second reflective layers define a laser cavity through the epitaxial electron beam responsive active gain layer therebetween. The electron beam source generates an electron beam which impinges on the epitaxial electron beam responsive active gain layer thereby generating a laser output. Accordingly, the single crystal active gain layer can be formed on the substrate by epitaxial deposition techniques increasing the performance and reliability of the electron beam pumped semiconductor laser.

Abstract: A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

Abstract: An improved sandwich layer of silicon dioxide layers for gap filling between metal lines. This is accomplished using a first layer formed in a PECVD process using TEOS and a fluorine-containing compound to give a barrier layer with a dielectric constant of less than 4.0, preferably approximately 3.5. Subsequently, an SACVD process is used with TEOS to form a gap filling layer. By appropriately choosing the thickness of the respective layers, one can adjust the dielectric to a value which is a combination of the dielectric constants of the two different layers, preferably giving a dielectric constant of approximately 3.6-3.7.

Abstract: A method for passivating a III-V semiconductor surface with Al.sub.2 O.sub.3 is disclosed. Sb-based semiconductor lasers may be etched with a solution of HCl:HNO.sub.3 :H.sub.2 O for a more uniform surface.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor.

Abstract: A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.

Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.

Abstract: A method of fabricating a semiconductor laser device is disclosed in which the device comprises one or more ion-implanted regions as a means to decrease the occurrence of device failures attributable to dark-line defects. The ion-implanted regions, which are formed between the laser gain cavity and the regions of probable dark-line defect origination, serve to modify the electrical, optical, and mechanical properties of the device lattice structure, thus reducing or eliminating the propagation of dark-line defects emanating from constituent defects or bulk material imperfections which may be present in the device.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. Thermal oxidation creates thick silicon oxide regions in areas of exposed doped polysilicon, while thinner silicon oxide regions form in areas in which the intrinsic HSG polysilicon spots are oxidized. Removal of both thick and thinner silicon oxide regions, creates the saw-toothed topography in the polysilicon storage node electrode, resulting in surface area, and capacitance increases.

Abstract: A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: By introducing an n-type drain implant substantially below the surface of the p-type substrate of a full frame image sensor, then enclosing the drain on the bottom and the sides with a deep p-type implant, and accumulating the surface with a shallow p-type implant, with all implantations performed through the same mask aperture, the blooming control, channel stop, and dark current suppression features of the imager are compressed, increasing the fill factor, facilitating pixel miniaturization, and therefore enabling high resolution imaging applications.

Abstract: Method of forming intermetallic insulating layers in semiconductor devices are disclosed, which not only have superior adhesion and homogeneous step coverage but also prevent the generation of voids due to the penetration of moisture. According to the method, metal interconnects are, first formed on the semiconductor substrate. Thereafter, a first insulating layer is formed to a thickness capable of sufficiently filling the spaces between the metal interconnects by reacting Tetraethylorthosilicate(TEOS) gas of a predetermined flow rate with O.sub.3 gas of a predetermined density in a CVD furnace. Next, a second insulating layer of a predetermined thickness is formed on the first insulating layer using the same furnace but by changing only the flow rate of TEOS.

Abstract: A process which prevents abnormal WSi.sub.x oxidation during subsequent LPCVD insulator deposition and gate sidewall oxidation, uses an in-situ deposition of a thin amorphous silicon layer on top of the tungsten silicide as well as the deposition of an amorphous spacer after gate stack patterning, respectively.

Abstract: An improved method of ozone-TEOS deposition with reduced pattern sensitivity and improved gap filling capability is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein the conducting lines are dense in some portions of the semiconductor substrate and sparse in other portions of the substrate and wherein gaps are formed between the conducting lines. A nucleation layer is formed by depositing a first pattern sensitivity reducing layer over the surfaces of the conducting layer and then depositing a first oxide layer overlying the first dielectric layer. A second oxide layer is deposited over the nucleation layer wherein the gap is filled by the second oxide layer and the fabrication of integrated circuit is completed.