Abstract: A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits.

Abstract: A method and apparatus are disclosed for managing a computer network. A manager software system is installed on a network management computer system within the network, and one agent software system is installed on each of the server computer systems in the network. A knowledge module in the form of a text fie is stored on the network manager computer system so that the manager software system can transmit knowledge to the various agent software systems throughout the network, for use by the agents in monitoring and managing the server on which they are installed. Interpretable script language programs are present on all computers in the network, expanding and customizing the functionality of the agent software systems. A method is disclosed for using the high level interpretable script language programs in connection with the agent software systems for discovering resources on the network, monitoring aspects of resources, and taking recovery actions automatically in the event of an alarm condition.

Abstract: A host adapter for transferring data between a system bus and an input/output (I/O) bus is implemented as an integrated circuit having a data transfer circuit and a status indicator circuit. The status indicator circuit selectively supplies one of a number of status signals from the data transfer circuit as a signal on a status indicator terminal of the host adapter. Therefore, a light emitting diode connected to the status indicator terminal indicates in real time the status of data transfer, such as usage of the system bus, or I/O bus, or execution time of one or more instructions by the host adapter.

Abstract: A versatile USB controller comprises a serial interface engine (SIE) for connection with a host. The SIE is capable of simulating a disconnect/connect sequence in situations where a reboot of the device is appropriate. The controller further includes a control store for keeping track of multiple endpoints of a device. A FIFO provides data transfer between each of the endpoints and the host. A state machine provides transaction sequencing with the host for each endpoint. In a variation of the preferred embodiment, a second FIFO is included to provide additional buffering capability.

Abstract: A data processing device having a DMA function for controlling DMA transfer, comprises a DMA unit, a CPU, a bus arbitration unit for controlling bus-using right of the DMA unit or the CPU, and an interruption controller for supplying an interruption request signal. The DMA unit includes a register, a comparator for making a comparison between a priority of a DMA transfer and a priority set on an interruption request, and a sequencer for deciding whether the DMA transfer is to be executed, canceled, or suspended in the operation state of a DMA unit according to the comparison result of the comparator.

Abstract: An automatic identification system in a computer system having a plurality of hardware instances located on hardware devices in the computer system. The computer system includes a plurality of physical slots each configured to receive a hardware device and referenced by a slot number. The system comprises means for assigning a hardware instance value to each of the plurality of hardware instances, the hardware instance value being unique within the computer system when two or more of the plurality of physical slots are assigned a slot number that is not unique within the computer system. Advantageously, the hardware instance value is unique within the computer system when two or more of the plurality of hardware instances are located on one of the hardware devices or when one or more of the hardware devices is installed in an expansion chassis coupled to the computer system.

Abstract: A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.

Abstract: A programmable configuration selector is provided to an apparatus having at least one configurable device. The programmable configuration selector comprises a non-volatile memory having at least one storage register for storing configuration information corresponding to the at least one configurable device, and a multiplexer driver. The multiplexer driver comprises at least one output port coupled to the at least one configurable device, for asserting configuration information, received from the non-volatile memory, on the at least one output port to configure the at least one configurable device at a first time, and for asserting operational data, received from a data bus, on the at least one output port to the at least one configurable device at a second time.

Abstract: The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

Abstract: An apparatus and the method for upgrading the firmware code of an optical disk drive via the ATA/IDE interface are disclosed. The optical disk drive has a firmware code memory and a microcontroller that executes the firmware code. A drive decoder decodes to connect the optical disk drive to a host computer system via the ATA/IDE interface. The apparatus includes a programming controller that receives signals from the ATA/IDE interface and performs input/output decode to determine whether the host computer system has requested an upgrade of the firmware or to maintain the optical disk drive in normal operation. A multiplexer has a first input connected to the programming controller, and the second input connected to the microcontroller. The multiplexer selects the first input to the memory device via the multiplexed output for performing a firmware upgrade operation when the host computer system requests a firmware upgrade.

Abstract: A method and system for transferring units of data between a computer memory and an external system in which a DMA controller stores and uses information from an I/O device interfacing with the external system to transfer data more efficiently.

Abstract: A system for facilitating, sending and receiving e-mail messages is disclosed. This e-mail system is supported by one or more main servers and a plurality of regional servers geographically distributed in populated areas, and are interconnected via a computer network such as the internet. An incoming e-mail message under this system is first processed and packaged by the main server to allow tracking of this message. The packaged message is then sent to the designated local server via a regional server. The local server receives the e-mail message and notifies or delivers the message to a client (user) e-mail device through one of several available notification methods. The e-mail device is a novel device designed to send and receive e-mail messages. It is a low cost device that may be a stand-alone device, a part of a multi-function device, or a part of a computer expansion card. The servers of the present invention can be maintained and operated remotely.

Abstract: A system and method that allows ISA-compatible DMA devices (60) to communicate over non-ISA buses such as the VL bus (20) and a PCI bus (30). In a computer system (10) with a non-ISA bus, the present invention couples a secondary set of DMA controllers (50) in the same input/output space and a glue logic circuit (70) to the non-ISA bus in the computer system (10) to allow the ISA-compatible DMA device (60) to operate over the non-ISA bus. The secondary set of DMA controllers (50) provides the support for an ISA-compatible DMA device (60) to perform DMA transactions and the glue logic circuit (70) directs the DMA controller accesses to the proper place in the computer system (10).

Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

Abstract: The present invention provides system managed buffering within a data storage system. In a preferred embodiment, when a user or application program makes an I/O request, the data storage system passes control to system managed buffering. System managed buffering queries the user or application request to see how the user/application will be reading or writing the data. Based on the intended use, the system and method disclosed herein allocates the buffers for the user or application based on the intended access to the data, the file size and optionally, the storage device attributes. Also in accordance with the objects of the present invention, the system and method provide for continuous improvement over the previous buffer allocations.

Abstract: The apparatus and method for high speed data and command transfer over an interface (202), such as an ISA or PCMCIA bus or interface, includes a transceiver (206) and a processor (210) having a direct memory access (DMA) controller (240), a memory (211) for storage of data, and a channel interface (218) for connection to a communications channel. The processor (210) is responsive through a set of program instructions, such as software or firmware, to receive an interrupt signal (310, 315) and, when the interrupt signal indicates a write command (320, 330), to transfer data via the transceiver from the interface to the memory for transmission over the communications channel (335), and when the interrupt signal indicates data received from the communications channel (350), the processor further responsive to generate a read command and transfer data from the memory to the interface via the transceiver (355).

Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.

Abstract: A method for queuing hardware control blocks, such as SCBs, for a system including a system processor coupled to a plurality of host adapter devices and a buffer memory controller device by an I/O bus is based on use of an endless new hardware command block queue, and an endless done hardware command block queue. The hardware command blocks for a plurality of devices, where each device includes a device processor, are managed by forming an endless queue for a device in a memory external to the device. A first pointer to the endless queue is maintained in a memory that is not within the memory space of the device processor. A second pointer to the endless queue is maintained in a memory addressable by the device processor. The first and second pointers address the head and tail hardware command block array sites of the endless queue.

Abstract: Data transmission control apparatus which controls data transmission between processing systems via a transmission line, each processing system including a memory system consisting of a main memory and a cache memory. The apparatus addresses data in the main memory by a memory address and gives an instruction to transmit the addressed data; determines whether or not the addressed data is in the cache memory; provides a match signal when the data is in the cache memory; reads the addressed data from the cache memory when instructed by the instruction and when a ready signal and the match signal are provided, and, otherwise reads the addressed data from the main memory; writes the data read into a port; transmits the data written in the port to the another processing system connected to the transmission line; and provides the ready signal when the port is ready to receive additional data.

Abstract: A federated system comprising a plurality of input/output circuit card assemblies and a Firewire or other daisy-chainable bus that provides low latency communication between a host computer and peripheral devices. A single circuit card assembly is used to interface to each peripheral device, and communication between the host computer and peripheral device may be made using a plurality of different communication protocols. The input/output circuit card assembly is daisy-chainable and incorporates circuitry that implements a bus constructed to Firewire (IEEE-1394) and other electrical specifications.