Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract: The system and method simplifies communication between a computer control program executing on the computer system and an input/output device coupled to the computer system and is independent of the privilege mode in which the computer program is executing and of the manner in which the input/output device is coupled to the computer system, namely directly such as via an expansion bus versus indirectly such as via a parallel port. An I/O manager provides input/output operation macros, comprising first and second conditional execution portions, along with other related functions. The computer program is compiled from one or more source code files, wherein the source code files employ the input/output operation macros and call other I/O manager functions.

Abstract: An output buffer circuit including different arrangements of output devices selectable by circuitry which tests the load characteristics to provide different buffer drive strengths, and different paths having different current carrying characteristics for enabling the output devices selectable by the circuitry which tests the load characteristics to vary the slew rate of the output devices to best match the load.

Abstract: A network system has a plurality of nodes interconnected to each other for transferring a data packet from a transmitting node to receiving nodes so as to concurrently drive the same. In the transmitting node, an estimating device estimates a time lag which exists between the transmitting node and each of the receiving nodes and which varies among the receiving nodes. A determining device detects a maximum one of the estimated time lags so as to set a reference time by which all of the receiving nodes can be synchronized with each other. A transmitting device transmits a data packet to the receiving nodes together with the reference time stamped on the data packet. In each of the receiving nodes, a receiving device receives the data packet together with the stamped reference time.

Abstract: An apparatus and method which overcomes connectivity limitations on PCMCIA and PC-CARD95 compatible devices by reconfiguring standard PCMCIA and PC-CARD pins for additional electrical interfaces. A detection circuit in the PC-card can detect the different interfaces. Once the different interfaces are identified, the connections to the receptacles of the PC-card connector are reconfigured such that the functional assignments of the receptacles conform with the requirements of each different interface. Thus, connection between different electrical interfaces to the physical interface of a PCMCIA-compatible device, without interference between them is possible.

Abstract: A multistage front end processor system combining a plurality of front end processors serially for executing complicated pre-processing. The plurality of stand-alone front end processors (6-1 to 6-n) are programs such as a penned character recognition program and a kana-kanji conversion program. A definition information storage module (7) may contain definition information on a composite front end processor composed of a plurality of stand-alone front end processors connected serially. A control module (9) references a definition information storage module (7) and, when a composite front end processor to be started is composed, for example, of a first-stage and a second-stage stand-alone front end processors (6-1, 6-2), sends data entered from an input device 1 to the first-stage stand-alone front end processor (6-1), sends its output to the second-stage stand-alone front end processor (6-2), and sends its output to an application program 10.

Abstract: A serial speed-matching buffer for transferring data signals between a selectable one of multiple transferring units to one or more receiving units. The serial speed-matching buffer has a plurality of registers which may each be selectably configured in load mode to receive data signals from selectable ones of the transferring units. Data signals provided to the speed-matching buffer from a selectable one of the transferring units may be made available to the receiving unit during the next clock period. This is an improvement over a rank-of-registers speed-matching buffer which generally inflicts a delay prior to the first word of any transfer. When not conditioned in load mode, each of the registers defaults to a serial chain mode in which data signals may be received from an associated adjacent one of the registers, and wherein a predetermined one of the registers provides data signals at the receiving rate.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.

Abstract: A communication interface unit (128) facilitates data word exchanges between a parallel driven bus (210) and a serial driven communication channel (136) by performing both parallel-to-serial and serial-to-parallel data conversion functions. A transmitter circuit (200) is included in the communication interface unit (128), which performs parallel-to-serial data conversion employing a multiplexer circuit (204) and control logic circuitry (208). The multiplexer circuit (204) concurrently receives a plurality of data bits of a data word being transferred, and the control logic circuitry (208) thereupon causes the plurality of data bits of the data word to be successively passed through the multiplexer circuit (204) so as to perform parallel-to-serial conversion. A receiver circuit (300) may also be included in the communication interface unit (128), which performs serial-to-parallel data conversion employing a plurality of flip-flops (304) and control logic circuitry (308).

Abstract: A network interface for coupling a computer node to a network has a physical interface which is coupleable to the network for coupling the network interface to the network. The network interface is coupleable to the computer node through a high-speed serial bus which has a latency and a signal transmission rate sufficient to enable transmission of signals between the network and the computer node without interim storage of the signals in a buffer on the network interface. In a preferred embodiment, the computer node has a processor capable of processing network protocols and the signals may be transmitted between the network and the computer node without processing of the network protocols by a processor on the network interface.

Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract: A method and apparatus for transferring data from a donor storage device to a target storage device in parallel with requests from a host computer for transfers between the host computer and the target storage device. A copy subroutine operates in response to background and foreground mode controllers. The background mode controller normally copies data from an initial position in the donor storage device sequentially by data block. When a DTR command from the host processor requests a data element from a block that has not migrated to the target storage device, the foreground controller uses the copy subroutine to transfer the designated block. The storage areas are divided into statistical blocks. If a threshold number of consecutive DTR commands accesses a particular statistical block, the system resets the parameters for the background mode controller to effectively move the copy subroutine to begin background copying from the statistical block.

Abstract: This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.

Abstract: There is disclosed an information processing apparatus, such as a printer, capable of selectively using plural control programs by utilizing an external memory, such as a program cartridge, containing additional programs. When a switching of control program is requested for example by a switch, the start address of the requested program is indirectly obtained by referring to a fixed address of the memory cartridge containing the requested program.

Abstract: A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors.

Abstract: Methods operable in a SCSI RAID subsystem to enable improved portability in host based RAID management programs. RAID management programs which provide an administrative user interface for managing the operation and configuration of a RAID subsystem have traditionally communicated with the RAID system using control function calls (ioctl) through the operating system's device driver. Ioctl function calls are notoriously non-standardized among different operating systems and even among different versions of certain operating systems. The methods of the present invention are operable within a RAID subsystem to enable use of standardized read and write system function calls to the device driver for communication with a control port within the RAID subsystem. A special LUN is reserved for such read and write administrative calls. The special control port LUN processes the read and write calls to perform the desired RAID management functions on behalf of the management program on an attached host computer.

Abstract: A companion computer system for a host computer wherein the host computer includes an interface for electrically and mechanically interfacing to the companion computer. An example is a PCMCIA slot. The companion system includes a PC card with an interface which mates with the interface on the host. A bus is located on the PC card. A CPU is located on the PC card and connected to the bus. A display is located on the PC card and connected to the bus. An input device is located on the PC card and connected to the bus. A non-volatile memory module is located on the PC card and connected to the bus. A low power random access memory module is located on the PC card and connected to the bus. A power supply is located on the PC card and connected to the components of the PC card An operating system is located in the non-volatile memory.

Abstract: An industrial controller having a number of addressable I/O modules, employs an I/O map table linking software addresses used for developing the control program to actual physical addresses of the I/O modules on a network. By employing software addresses for connection points to the control process, the program may be developed independent of the topology of the network connecting the processor to the I/O modules and changes in that topology may be made without affecting the control program, but simply by changing the I/O map table. A single change in the I/O map table re-connects an I/O module for all references in the control program.

Abstract: A policy caching method for use in a communication device is provided. The communication device determines which instance of protocol data unit (PDU) network policy from a plurality of policies is to be applied to related-received PDUs based on contents of one of the related-received PDUs. Subsequently, policy identification information identifying the instance PDU policy is cached for future application to other of the related-received PDUs. Also, a communication device which implemented this policy caching method is provided.

Abstract: A large-scaled interconnection switch in which a plurality of data processors are interconnected to perform data transfer between one another. The switch includes communication controllers, one provided for each of the plurality of data processors, divided into groups, for controlling communication between the data processors. Each group of communication controllers is connected by a signal line having a multiple bit width. A switch arbiter for arbitrates switch setting requests for interconnection of the data processors from the communication controllers to output a switch setting control signal. The switch also includes bit slice switches having a predetermined bit division count and to which respective/output signal lines are connected which bit-divide input/output signals of the communication controllers.