Abstract: A method for emulating programs in a system includes a plurality of first and second data processors having different instruction word sets. An instruction which interrupts the operating system on the first data processor is defined. When the instruction is detected in a program running on the first data processor, it is determined whether or not the instruction is an instruction associated with an input/output macro instruction. If it is found, as a result of the determination, that this is the case, an interrupt is caused in a program running on the second data processor which controls the emulation, and the input/output macro instruction output from an emulated program is translated into an input/output macro instuction for the operating system, thereby implementing an emulation with a minimized overhead.

Abstract: A dual mode disk controller is disclosed for use between a host processor and its storage medium for controlling data transfer to and from the storage medium. The data is formatted on the medium in two distinct formats, one capable of bulk fast transfers useful in a swapping operation, and the other capable of periodic slower transfers as is acceptable for file retrieval. The disk controller is designed having a small fast buffer memory for accepting information from the storage medium. File transfer data is transferred immediately without host CPU intervention, to a larger cache memory. The host CPU accesses the fast buffer memory periodically to retrieve swap transfer data while only accessing the larger cache memory when it needs to retrieve the file formatted information.

Abstract: A method and apparatus for access to a programmable controller at a remote location. A peripheral device with a peripheral processor is connected to a port on an I/O module. Blocks of discrete and block transfer data are transferred to and from a common memory in the I/O module where the data is accessible to a serial communication controller that interfaces the module to a high speed serial data channel. Asynchronous communication is provided between the serial communication controller and the peripheral device using a circular buffer in the common memory. Timing considerations are also disclosed.

Abstract: The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.

Abstract: A microcomputer provided with a direct memory access (DMA) controller comprises a central processing unit (CPU), which includes a CPU timing controller, an address computation section, and an address bus output buffer coupled between the output of the address computation section and an external address bus. The CPU also includes an auxiliary timing controller operative, in response to a hold request from a DMA controller, to output a HOLD acknowledge (HOLDA) signal to the DMA controller and to reset a BUS ENABLE signal to the address bus output buffer, so tha the CPU is isolated from the external address bus. The CPU further includes an address latch circuit connected between the output of the address computation section and the address bus output buffer to temporarily hold the address output in response to a latch signal from the auxiliary timing controller, so that the address output is supplied to the address bus immediately when the latch signal is reset at the termination of the DMA operation.

Abstract: A memory control device which is able to interface with any memory regardless of the address information format for reading out data stored therein. The memory control device includes an address generator for generating address information for reading out corresponding data from the memory device, a data processing circuit such as a microprocessor for processing the stored data, a first bus for transmitting the stored data from the memory device to the data processing circuit, a second bus for transmitting address information generated by the address generator to the memory device, a third bus for selectively transmitting either the stored data to the data processing circuit or transmitting address data to the memory device, a mode signal generator for generating a mode signal, and a control circuit connected between the mode signal generator and the third bus for controlling the selective data transmission of the third bus in response to the mode signal.

Abstract: A method is disclosed for processing instructions in higher level virtual machines by a 370-XA mode real machine. The real machine and a low level virtual machine each execute a version of the real machine's system control program. The low level virtual machine issues a privileged (SIE) instruction which is simulated by the real machine indicating that instructions in a higher level virtual machine are to be processed. A shadow state description is created and used by the privileged instruction for describing the higher level virtual machine directly to the real machine. Shadow address translation tables are also created in the case when the higher level virtual machine is a pageable machine so that interpretive execution hardware, invoked by the privileged instruction, can translate through the higher level virtual machine translation tables followed by translation through the shadow translation tables.

Abstract: A vector processor for sequentially reading out elements of a plurality of vector operands and sequentially storing the results of operations to the vector operands, comprising: operand counters for indicating the element numbers for every operand; address registers for every operand; a first comparator for comparing each element of the vector; maximum number registers for storing the maximum numbers of elements of the respective operands; a second comparator for comparing the operand counter of each operand with the content of the maximum number registers of each operand with respect to each operand; and a control circuit for independently updating the operand counters and operand address registers of ech operand in response to all of or parts of the outputs of the first and second comparators.

Abstract: A vector processing apparatus has a number of pipeline arithmetic units operating concurrently to execute a set of vector instructions dealing with vector elements. Stack registers are provided for each arithmetic unit to hold the vector instruction address, leading vector element position and vector register internal address, so that one of the exceptions that can be detected successively by several arithmetic units during the process of the vector instructions is selected on a priority basis through the comparison of information in the stack of the currently detected exception with information of exception detected previously.

Abstract: There is provided a vector processor based on a pipeline control method in which a cyclic operation is divided into a plurality of stages and processed. This processor comprises a vector register controller for dividing an operating process into a plurality of fundamental process units and controlling these units, and a phase generator for allowing the vector register controller to time-sharingly make the vector processor operative. This vector processor reads out data from vector registers in which vector elements are stored, operates this data and writes the result of operation into the vector register. With this vector processor, a cyclic operation can be processed in parallel at a high speed without causing a remarkable increase in hardware.

Abstract: In a vector processing unit, a vector register undergoing the first readout operation is simultaneously subjected to the second reading operation. The data obtained by the first readout operation and the data obtained by the second readout operation are respectively sent to separate resources executing different instructions.

Abstract: Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching the unoperational state detection task running on the n-1 priority level at time intervals smaller than a specified time-out delay. A detection timer (1) is set at an initial value each time the task is dispatched and the content is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and is reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.

Abstract: A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

Abstract: A priority resolution device for bus orientated computer systems. The system includes a plurality of subsystems, each connected to an associated logic circuit, as well as structure for periodically assigning to each of the subsystems together with input to the logic circuit associated therewith a priority indicating an n-bit digital signal. Sets of n signal lines are provided, one set connected to each logic circuit to carry a corresponding bit of the n-bit signal, ranging from the most significant bit (MSB) to the least significant bit (LSB). An open collector bus has n bus lines, each connected to a corresponding one of the signal lines.

Abstract: A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.

Abstract: The disclosure relates to a memory mapping system wherein information is stored on a page by page basis in memory in discontiguous locations therein with the address of the next page in which storage is to take place always being available in the controller to minimize delay in storage from the end of one page to the beginning of the following page, regardless of page location in memory. When a user makes a request for storage space in memory, the amount of memory required is determined and the host looks to see where it can obtain that memory. Typically, use of discontiguous memory locations is required. All of the information relative to the addresses of the discontiguous storage locations in memory is provided to the controller by the host computer in a single command rather than after each move to a discontiguous storage location. All jumps to discontiguous storage locations are then performed independent of the host computer.

Abstract: At the point of time at which a segment base address is generated in current loop processing, a segment address displacement for use in the next loop processing is calculated in advance and held in one of a plurality of address registers, thereby to shorten the period of time required for address generation and to permit an overlap in the loop processing. Besides, in order to permit an overlapping in the loop processing even in a case where address registers of identical number are shared for effective utilization among different instructions, (n+1) groups of address registers are provided, and the overlapping of operations can be realized among the n successive loop processings.

Abstract: A microcomputer unit containing therein a plurality of registers each with an address allotted in advance. The registers can be accessed for monitoring by an external address signal when the allotted address thereof and the external address signal coincide with each other. In this case, operation of the microcomputer is stopped by an external HALT signal and then the content of the register to be monitored is read by a monitor (MNT) signal MNT, so that the content thereof is fed externally from the microcomputer unit.

Abstract: In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.

Abstract: The individual RAMs comprising the memory space of a computer may be of various sizes and are automatically located within a memory space during initialization and address enable information is stored in ID-RAMs on each RAM card. Shift registers on the RAM cards are connected in series and an ID bit is serially clocked through the shift registers during initialization. At each clock pulse the contents of the shift registers are written to the ID-RAMs of each RAM card. The presence of an ID bit at a specific memory location in an ID-RAM on a RAM card indicates that card is to be enabled when the memory location address is accessed; the location of the ID bit within the memory location indicates the particular RAM on the RAM card to be accessed. A detector monitors a transfer of the ID bit between adjacent shift registers so that card memory boundaries, and RAM size, may be known.