Abstract: An address conversion unit for a multiprocessor system including a common memory, and in which at least one processor includes a private memory, with the private memory and common memory having separate and distinct memory spaces. The conversion unit converts addresses between private addresses that are used within the processor itself and addresses that are used to retrieve contents of locations in common memory.

Abstract: When a CPU accesses a memory device, the upper address data of an address signal is transmitted as parallel signals while the upper address data thereof is transmitted as serial signals after parallel-serial conversion. In order to convert the upper address into the serial signals, a parallel-serial converter is disposed on the side of the CPU or on the side of the CPU of an address bus while a serial-parallel converter is disposed on the side of a memory device or on the side of the memory device of an address bus. The signal lines of the address bus can be decreased in number.

Abstract: The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.

Abstract: The disclosure relates to demotion of data to a backing store (disk storage apparatus--DASD) from a random access cache in a peripheral data storage system. A cache replacement control list, such as a least recently used (LRU) list is scanned in a soon-to-be replaced first portion (portion closest to LRU entry) to identify first data to be demoted. Then the control list is scanned in first and second portions to identify further data to be demoted with the first data as a single group of data. In DASD, such data is all storable in the same cylinder of the DASD.

Abstract: A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the central storage facility directly to the instruction register for bypassing the instruction buffer when certain special instructions being held in the instruction register are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction.

Abstract: A multimicroprocessor system constructed of multimicroprocessor structures each including N-number of microprocessor units, a shared memory, an input/output unit and a register exchange circuit. The microprocessor units are uniform and include a microprocessor, a data memory, a parallel input-output interface, a sequential input/output circuit, a program memory and a bi-directional buffer. The buffer connects the internal data bus in the microprocessor unit to the shared instruction bus for the multimicroprocessor structure, and the enable inputs of the buffer are connected to the internal busses for circuit selection in the microprocessor unit by the microprocessor address lines.