Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

Abstract: The present disclosure provides an integrated circuit device comprising a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature over the semiconductor substrate; semiconductor layers connecting the first source/drain feature and the second source/drain feature, the semiconductor layers stacked over each other along a first direction normal to the top surface; each of the semiconductor layers having a center portion of a first thickness and two end portions of a second thickness larger than the first thickness; each of the two end portions connecting the center portion and one of the first and the second source/drain features; a gate electrode engaging the center portion of each of the semiconductor layers; a first spacer over the two end portions of a topmost semiconductor layer of the semiconductor layers; and a second spacer between vertically adjacent end portions of the semiconductor layers.

Abstract: A semiconductor device includes a substrate with an isolation region surrounding a P-active region and an N-active region, a first gate electrode comprising a first metal composition over the N-active region, and a second gate electrode with a center portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes a first metal composition, and the center portion includes a second metal composition different from the first metal composition, and the center portion and the endcap portion do not overlap. An inner sidewall of the endcap portion is substantially aligned with a sidewall of the isolation region.

Abstract: At least one array of LEDs (e.g., in a flip chip configuration) is supported by a substrate having a light extraction surface overlaid with at least one lumiphoric material. Light segregation elements registered with gaps between LEDs are configured to reduce interaction between emissions of different LEDs and/or lumiphoric material regions to reduce scattering and/or optical crosstalk, thereby preserving pixel-like resolution of the resulting emissions. Light segregation elements may be formed by mechanical sawing or etching to define grooves or recesses in a substrate, and filling the grooves or recesses with light-reflective or light-absorptive material. Light segregation elements external to a substrate may be defined by photolithographic patterning and etching of a sacrificial material, and/or by 3D printing.

Abstract: A phase-change material based resistive memory contains a resistive layer and two electrical contacts. After fabrication the memory is subjected to thermal treatment which initiates a transition toward a crystalline state favoring in this way the subsequent obtaining of a large number of resistive memory states.

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Abstract: A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a metalorganic precursor, the metalorganic precursor comprising a metal selected from the group consisting of a cobalt, nickel, tungsten, molybdenum, manganese, iron, and combinations thereof. The method may also include; contacting the substrate with a second vapor phase reactant comprising ruthenium tetroxide (RuO4); wherein the ruthenium-containing film comprises a ruthenium-metal alloy. Semiconductor device structures including ruthenium-metal alloys deposited by the methods of the disclosure are also disclosed.

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

Abstract: Provided is a backlight module including a light source, a light guide plate, and a composite color-conversion layer. The light source emits a blue light. The light guide plate is optically coupled to the light source and the blue light transmits through the light guide plate. The composite color-conversion layer is disposed on the light guide plate. The composite color-conversion layer includes at least three different populations of quantum dots. The at least three different populations of quantum dots at least include a plurality of cyan quantum dots or a plurality of yellow quantum dots.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A method for forming fins of Fin FETs is provided. A patterning process on the second sidewalls forms a type-one second sidewalls and a type-two second sidewalls, the type-one second sidewalls are arranged next to each other and sandwiched between a pair of type-two second sidewalls on one side and another pair of type-two second sidewalls on another side, followed by an etching to remove the pairs of the type-two second sidewalls from both sides of the type-one second sidewall. The type-two second sidewalls adjacent to the two sides of the type-one second sidewalls are not pattern-transferred to a to-be-patterned layer, after the fin patterns on the to-be-patterned layer are formed, patterns corresponding to the type-two second sidewalls are etched away through a rough removal process.

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.

Abstract: A method for manufacturing a fin field-effect transistor is provided, comprising making metal gates, a gate dielectric layer, and a work function layer of the metal gate structures, followed by removing a portion of the end of each of the metal gates that protrudes from a fin region. Since the work function layer is already formed by the removing step, the process window of the work function layer is not affected. Therefore, a relatively large edge region of the metal gates can be removed, thereby minimizing the parasitic capacitance Cgs between the gate and the source or parasitic capacitance Cgd between the gate and the drain of a fin field-effect transistor device in operation. Meanwhile this step simplifies and compatible with the finFET process.

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

Abstract: A semiconductor device includes a semiconductor substrate, first gate structure, a first metal layer, a first protective layer, and a first contact plug. The first gate structure includes a plurality of first U-shaped layers stacked one another between the first gate spacers in a cross-sectional view and first gate spacers on opposite sides of the first U-shaped layers. The first metal layer is over the first U-shaped layers and has a different shape than the first U-shaped layers in the cross-sectional view. The first protective layer is over the first metal layer and between the first gate spacers. The first contact plug extends through the first protective layer and the first metal layer, and is in contact with the first gate structure.

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.