Abstract: A motherboard may utilize a retimer device to condition signals used for high-speed USB data transfers. Motherboard embodiments include a common footprint for USB retiming capabilities. A motherboard that supports high-speed USB transfers, such as transfers of 10 Gbps or greater, utilizes a retimer in the footprint. A motherboard that supports lower-speed USB transfers, such as 5 Gbps, utilizes a passive bridge component in the footprint, where the bridge may be formed from a dielectric substrate. During manufacture of an IHS (Information Handling System) a common motherboard is selected that includes a retimer footprint, where the motherboard includes traces that couple the footprint to a USB connector and traces that couple the footprint to a USB controller. Based on the USB transfer speeds to be supported by the motherboard, a USB retimer or a passive bridge is installed in the retimer footprint.

Abstract: An information handling system may include at least one processor; a slot configured to receive an information handling resource and couple the information handling resource to a communications bus of the information handling system; and a computer-readable medium having instructions thereon that are executable by the at least one processor. The instructions may be executable for determining logical states for a plurality of pins of the slot; based on the determined logical states, determining a communications width associated with an information handling resource received in the slot; and setting a bifurcation variable associated with the slot based on the determined communications width.

Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger transfer of said user selected arbitrary media content to said transmitter.

Abstract: A rack switch coupling system includes computing devices positioned in a rack in a stacked orientation. A switch system positioned in the rack includes a circuit board with a processing system. Respective first ports are each located on the circuit board, coupled to the processing system via a respective trace on the circuit board, cabled to a respective one of the computing devices, and located adjacent its cabled computing device between a top plane and a bottom plane associated with that computing device. Respective second ports are each located off of the circuit board, coupled to the processing system via a respective trace on the circuit board and a respective cable extending between that trace and that second port, cabled to a respective one of the computing devices, and located adjacent its cabled computing device between a top plane and a bottom plane associated with that computing device.

Abstract: Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master device—of a plurality of master devices coupled to a respective plurality of slave devices via an internal network—may implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

Abstract: In one example, a data processing unit (DPU) includes a host unit interface for communicatively coupling to second device via a serial input/output (I/O) connection, and a control unit implemented in circuitry and configured to initially configure the host unit interface of a data processing unit to operate in endpoint mode, determine that the host unit interface of the data processing unit is to switch from operating in the endpoint mode to root complex mode, in response to determining that the host unit interface is to switch from operating in the endpoint mode to the root complex mode: configure the host unit interface to operate in the root complex mode, and send data to an I/O expander unit to cause the I/O expander unit to issue a reset signal to the second device, the second device being configured to operate in the endpoint mode.

Abstract: A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

Abstract: Technology allowing for easy access to connectors in a patch panel. In one of the configurations a patch panel includes at least one patch panel subassembly, each patch panel subassembly including at least one mounting plate and a plurality of port assemblies, the at least one mounting plate being configured to accommodate the port assemblies so that each port assembly can individually translate along a direction parallel to a surface of the mounting plate and can rotate about an axis perpendicular to the surface of the mounting plate.

Abstract: A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.

Abstract: A method includes presenting a graphical user interface to a user, where the graphical user interface identifies multiple slots that are configured to be coupled to multiple input/output (I/O) modules. The method also includes receiving, from the user via the graphical user interface, information defining a slot assembly data map. The slot assembly data map identifies data offsets and data sizes associated with the I/O modules. The data offsets and the data sizes identify where data can be sent to or received from the multiple I/O modules over a single logical connection. The method further includes using the data offsets and the data sizes of the slot assembly data map to provide data to or receive data from one or more of the I/O modules over the single logical connection.

Abstract: In an asynchronous channel based bus architecture enabling decoupled services, there is an asynchronous channel based bus having at least one channel. A first service is coupled to the asynchronous channel based bus, the first service passes messages to and receives messages on the at least one channel. A second service is also coupled to the asynchronous channel based bus, the second service also passes messages to and receive messages on the at least one channel.

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A method for the initial programming of a secondary computer. The method includes configuring a serial interprocessor interface between the secondary computer and a main computer, and data are written via the interface to a flash memory of the secondary computer.

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Abstract: An electronic device is disclosed. The electronic device comprises: a housing, an input/output interface, which includes a plurality of pogo pins exposed through a portion of the housing, and can be connected to an external device by a wire, an identification circuit, which is electrically connected to the input/output interface to identify the external device, a processor electrically connected to the identification circuit, and a booster electrically connected to the input/output interface to supply power to the external device. In addition, various embodiments understood from the specification are possible.

Abstract: A display device for process automation includes a display unit, a controller, a current loop interface and a fieldbus interface. The display device is designed for power supply via the current loop interface, and the controller is designed to assign an analog coded signal of an output data present at the current loop interface to a first input data and to display the first input data via the display unit. The controller is designed to request the transmission of the output data in the form of a digitally coded signal via the fieldbus interface, to receive the digitally coded signal via the fieldbus interface, to assign the digitally coded signal to a second input data, to perform a comparison between the first input data and the second input data, and to display a result of the comparison via the display unit.

Abstract: Methods involve distributing a data stream in a value-document processing apparatus from at least one sensor to at least one processing unit and a system for distributing sensor data. The value-document processing apparatus has a distributing device and at least one processing unit. The distributing device comprises at least two data interfaces. A sensor data packet is created and comprises the sensor data and a target address. The target address describes a physical memory address of the at least one processing unit. The sensor data packet is sent to one of the data interfaces of the distributing device. The distributing device receives the sensor data packet at a further data interface. The sensor data packet is relayed by the distributing device to the at least one processing unit.