Patents Examined by Christopher Shin
  • Patent number: 10152442
    Abstract: In one general aspect, a method can include determining an orientation of a plug inserted into a connector included in the computing device, providing a plurality of display data signals to a reordering switch included in the computing device, selecting, by the reordering switch and based on the determined orientation of the plug, a display data signal from the plurality of display data signals, providing the selected display data signal to at least one of a plurality of multiplexers, the plurality of multiplexers being orientated back-to-back, providing a data signal to the at least one of the plurality of multiplexers, enabling the at least one of the plurality of multiplexers, selecting the display data signal for output by the at least one of the plurality of multiplexers, and providing the selected display data signal to a contact included on the connector.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 11, 2018
    Assignee: GOOGLE LLC
    Inventors: Andrew Bowers, James Tanner, Joseph Edward Clayton, Mark D. Hayter, Christopher Lyon, David Ness Schneider
  • Patent number: 10102166
    Abstract: The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 16, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenji Kimura
  • Patent number: 10089249
    Abstract: An apparatus, shipping container, and system for in-package storing of data for an electronic device are disclosed. In one example, the apparatus comprises an electronic device that has a housing and is packaged in a shipping container that substantially encloses the electronic device. The housing includes a first communication interface and the shipping container includes a second communication interface. The second communication interface is in electrical communication with the first communication interface such that power and data signals can be communicated via the first and second communication interfaces between the electronic device and another electronic device located outside the shipping container.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: October 2, 2018
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventors: Steve A. Doria, John J. Manatt
  • Patent number: 10083149
    Abstract: The disclosure relates to a method for serially transmitting frames from a transmitter to at least one receiver via a bus line and to a participant station for a bus system. In the method, stuff bits are integrated into the frame by the transmitter dependent on the values of multiple previous bits in order to generate additional signals edges. The transmitter of the frame counts the stuff bits which are integrated depending on the value of multiple previous bits, and information on the number of counted stuff bits is transmitted in the transmitted frames.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 25, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Florian Hartwich, Franz Bailer, Arthur Mutter, Jan Scheuing
  • Patent number: 10083145
    Abstract: A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th processor pin sets of the CPU are switchably electrically connected to 1st to a-th first PCI-E pin sets of the first PCI-E slot or (2N?a+1)th to 2N-th second PCI-E pin sets of the second PCI-E slot via the first switch to form PCI-E lanes whose number is a. (a+1)-th to 2N-th processor pin sets of the CPU are connected to the second input terminal of the second switch, and the second output terminal of the second switch is switchably electrically connected to (a+1)-th to 2N-th first PCI-E pin sets of the first PCI-E slot or 1st to (2N?a)th second PCI-E pin sets of the second PCI-E slot to form PCI-E lanes whose number is 2N?a, wherein 1<a<2N.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 25, 2018
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Pei-Hua Sun, Hon-Yeh Lee, Yen-Yun Chang
  • Patent number: 10078613
    Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 18, 2018
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Carl G. Ramey
  • Patent number: 10078465
    Abstract: Aspects of the present disclosure involve a system architecture for a policy driven disk IO throughput control for a hyper-converged storage provider. The computing architecture provides a flexible and real-time feature to the IO throughput management of a hyper-converged or converged infrastructure. In particular, through the use of centrally applied policy driven controls, the disk IO throughput allocation of different applications/clients of the converged infrastructure is gauged or otherwise controlled over the network bandwidth that link to the storage pool of the infrastructure. Through the use of the system architecture, the converged infrastructure may not utilize hard-coded disk resource allocation for each application/client in an isolated fashion, thereby allowing the IO throughput management to be flexible and agile in response to executed applications. Further, the IP throughput controlling and storage IP capacity of the converged infrastructure may be maintained separately.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 18, 2018
    Assignee: VCE IP Holding Company LLC
    Inventors: Jiatai Wu, Rama Krishna Gurram, Krishna Kattumadam
  • Patent number: 10078363
    Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Patent number: 10078615
    Abstract: A method of operation in a system is disclosed. The system includes a system processor, main memory coupled to the system processor, and a serial input/output (IO) interface coupled to the processor. The method includes de-framing multi-media packet data with a local area network peripheral device such as Ethernet, the multi-media packet data having a timing reference. The packet data is mapped to the main memory with the Ethernet peripheral device. The multi-media packet data is then transferred to the main memory as multi-media data, and stored in storage locations of the main memory in accordance with the mapping. The mapping information is accessed from device Host operating system with a second peripheral device via the serial I/O interface. The second peripheral device directly accesses the main memory storage locations. Significant power savings is realized for the CPU.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: September 18, 2018
    Assignee: Aquantia Corp.
    Inventors: Simon Edelhaus, Alexey Andriyanov
  • Patent number: 10078614
    Abstract: Data transfer between a data storage device and a peripheral device bypasses an application processor that is coupled to the data storage device and to the peripheral device. In one embodiment, the data storage device includes a memory controller configured to receive, from an application processor, a message indicating a set of logical addresses and a data transfer identifier corresponding to the set of logical addresses. The memory controller is responsive to a request for memory access that includes the data transfer identifier and that is received from a peripheral device. The memory controller is configured to respond to the request by performing a memory access operation based on the set of logical addresses.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: September 18, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eliad Adi Klein, Rotem Sela, Miki Sapir
  • Patent number: 10067894
    Abstract: The following description is directed to cable-based configuration. In one example, a method can include determining a first end of a cable is connected to a first device and a second end of the cable is connected to a second device. The first device can be configured to perform a first function when it is determined the first end of the cable is connected to the first device. The second device can be configured to perform a second function when it is determined the second end of the cable is connected to the second device. The second function can be different from the first function, such that the first device and the second device are configured differently based on which end of the cable is connected to the respective device.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: September 4, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason Alexander Harland, Ziv Harel, Darin Lee Frink
  • Patent number: 10061727
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 10061599
    Abstract: Firmware determines during a boot of a computer, if a bus enumeration is needed or if the computer can be booted quicker by skipping a bus enumeration. The firmware performs a bus enumeration if this a first boot or if the bus has had it infrastructure changed since the previous boot. For buses that have only fixed resources coupled to it, then the bus configuration cannot change. Also, for buses that do not have only fixed resources, the infrastructure may be probed to determine if the bus configuration has changed. If there is no change, bus enumeration is not needed. Metadata is created, updated and stored in flash memory involving the bus infrastructure. Since the metadata is stored, a bus enumeration is not needed to gather information about the bus when no change has occurred.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 28, 2018
    Assignee: American Megatrends, Inc.
    Inventor: Sergiy B. Yakovlev
  • Patent number: 10055368
    Abstract: A mobile device and method for synchronizing use of the mobile device's communications port among a plurality of applications are provided. In one embodiment, a mobile device is provided comprising a communications port configured to connect with a mobile device accessory and a processor. The processor is configured to synchronize requests from a plurality of applications running on the mobile device to prevent application(s) from sending a request that would interrupt an ongoing data transfer between the mobile device accessory and another application. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 21, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Anurag Chelamchirayil Muraleedharan, Eyal Hakoun
  • Patent number: 10049060
    Abstract: A semiconductor device includes a processor for running a real-time operating system (RTOS). The RTOS causes the processor to update internal time during a first mode and to stop updating in a second mode. A first counter periodically transmits an interrupt signal to the processor that is coordinated with a periodic counting sequence. A second counter counts while the semiconductor device is in the second mode. A first circuit reads a first count value from the first counter at a starting time of a transition from the first to the second mode, masks the interrupt signal, and causes the second counter to start counting. A second circuit unmasks the interrupt signal from the first counter after a starting time of a transition from the second to the first mode and reads a second count value from the second counter.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 14, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeaki Takaki
  • Patent number: 10037299
    Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 31, 2018
    Assignee: Mellanox Technologies Ltd.
    Inventors: Carl G. Ramey, Christopher D. Metcalf
  • Patent number: 10013366
    Abstract: The present disclosure relates to a standardized hot-pluggable transceiving unit executing a web server function for controlling the transceiving unit, and a method and computer program product for controlling the transceiving unit through the web server function. The method comprises executing by a control unit in the housing of the transceiving unit a web server function, receiving via a communication interface of the transceiving unit a control command, processing the control command by the web server function, and configuring a component of the transceiving unit based on the processing of the control command. The configured component may be the control unit or a signal processing unit. The method may further comprise generating a diagnostic message by the web server function, which is transmitted to a control device via the communication interface. The diagnostic message may comprise a diagnostic of the control unit or the signal processing unit.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 3, 2018
    Assignee: EMBRIONIX DESIGN INC.
    Inventors: Renaud Lavoie, Eric Dudemaine
  • Patent number: 10013215
    Abstract: A method of transparently inserting a virtual storage layer into a Fiber channel based storage area network (SAN) while maintaining continuous I/O operations is provided. A device is inserted between a host entity and a first storage device. The device identifies a plurality of first paths between the host entity and the first storage device, and defines a plurality of second paths by defining, for each first path among the plurality of first paths, a corresponding second path between the host entity and a second storage device. The device determines, for each of the plurality of first paths, a respective first state. The device establishes, for each of the second paths among the plurality of second paths, a second state based on the first state of the corresponding first path. The device redirects, to the second storage device, communications directed from the host entity to the first storage device, via the plurality of second paths.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 3, 2018
    Assignee: Cirrus Data Solutions, Inc.
    Inventors: Wayne K. Lam, Wai T. Lam, Yikshum Tam, Lin Zhu
  • Patent number: 10013328
    Abstract: A method is provided for indicating to a user that a sink device is incorrectly connected to a High Definition Multimedia Interface (HDMI) In port. In accordance with the method, a proxy voltage is applied from an HDMI In port over an HDMI cable. The proxy voltage is sufficient to cause a hot plug event to occur. A hot plug event condition is detected at the HDMI In port from a device that is connected to the HDMI In port via the HDMI cable. Extended Display Identification Data (EDID) is read from the device at the HDMI In port over the HDMI cable. In response to receipt of the EDID, a determination is made that the device is a sink device and an error message is generated in response to the determination.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 3, 2018
    Assignee: ARRIS Enterprises LLC
    Inventors: Charles Hardt, John P. Eck
  • Patent number: 10013173
    Abstract: An electronic device including a communication interface and a command buffer coupled to the communication interface. The communication interface is configured to receive commands from a plurality of initiator devices, and the command buffer is configured to store the commands. The electronic device further includes a command buffer management module coupled to the command buffer. The command buffer management module is configured to generate a message indicating a remaining allowed storage size associated with the command buffer. The communication interface is further configured to enable communication of the message to a particular initiator device of the plurality of initiator devices. The message may enable the particular initiator device to hold off on sending one or more other commands to the command buffer if the remaining allowed storage size fails to satisfy a threshold storage size.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 3, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shankar More, Kapil Sundrani