Patents Examined by Christopher Shin
  • System-on-chip having special function register and operating method thereof
    Patent number: 9384855
    Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Han Lee, Eun-Ji Kang, Jae-Sop Kong, Kee-Moon Chun
  • Optimum cache access scheme for multi endpoint atomic access in a multicore system
    Patent number: 9372796
    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D Pierson
  • Expansion card
    Patent number: 9367507
    Abstract: An expansion card includes a peripheral component interconnect express (PCIe) slot, a PCI expansion controller, a PCIe/serial advanced technology attachment (PCIe/SATA) converter, a hard disk drive (HDD) controller, and a storage chip. An edge connector is arranged on a bottom side of the expansion card and includes power pins, ground pins, and signal pins. The power pins are connected to power pins of the PCIe slot, the PCIe expansion controller, the PCIe/SATA converter, the HDD controller, and the storage chip. The signal pins are connected to the PCIe expansion controller. The PCIe expansion controller expands a PCI signal into PCI signals and provides the PCI signals to the PCIe slot and the PCIe/SATA converter. The PCIe/SATA converter converts the PCI signal to SATA signals and provides the SATA signals to the HDD controller. The HDD controller controls the storage chip to read or write data.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: June 14, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Meng-Liang Yang
  • PCIe SMBus slave address self-selection
    Patent number: 9355053
    Abstract: Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon initialization. Embodiments of the invention describe logic/modules to retrieve a first SMBus slave address included in non-volatile memory for a slave device, wherein said slave device is communicatively coupled to a host system via an SMBus. A first message (e.g., a ping) is transmitted to the first SMBus slave address via the SMBus. If a response to the first message is not received, the first SMBus slave address is selected for the slave device. If a response to the first message is received, the first SMBus slave address is changed by an offset value to determine a second SMBus slave address for transmitting a second message via the SMBus.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventor: Christopher N. Bradley
  • Dynamic distribution of replicated data
    Patent number: 9342250
    Abstract: A system and method for data storage. The method can include: identifying, by a computer processor, a cluster map representing a set of storage resources; for each storage resource of the set of storage resources: traversing, by the computer processor, the cluster map to map the storage resource to a candidate resource set including at least one other storage resource of the set of storage resources; identifying a first data object associated with a storage request; identifying a first candidate resource set based on the first data object; and selecting a first final resource set based at least on the first candidate resource set, where the first data object is sent to storage resources of the first final resource set for storage.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 17, 2016
    Assignee: Twitter, Inc.
    Inventors: Peter Schuller, Christopher Goffinet, Sangjin Lee, Meher Anand, Edward Ceasar, Armond Bigian
  • Memory channel that supports near memory and far memory access
    Patent number: 9342453
    Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
  • Method and apparatus for managing memory
    Patent number: 9335946
    Abstract: A method includes, if functional units assigned with multiple reserved areas is not driven, storing data with one of a data withdrawal condition set in the multiple reserved areas, and if the functional unit is driven, processing data stored in the one of the multiple reserved areas to restore the multiple reserved areas for driving the functional units based on the one of the data withdrawal condition set. An apparatus comprises a memory including multiple reserved areas and multiple non-reserved areas, wherein if a functional unit assigned with one of the multiple reserved areas is not driven, data is stored in the one of the multiple reserved areas with one of a data withdrawal condition set, and when the functional units is driven, data stored in the one of the multiple reserved areas is processed to restore the one of the multiple reserved areas.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee-Sub Shin
  • Universal serial bus signal test device
    Patent number: 9323707
    Abstract: A universal serial bus (USB) signal test device includes a printed circuit board. A first connector, a second connector, and a number of USB hub integrated circuit (ICs) are arranged on the printed circuit board. The USB hub ICs are connected in series. A USB signal is passed through the USB hub ICs and an auxiliary test device in that order. The USB signals are measured with an oscilloscope after being passed through the USB hub ICs and the auxiliary test device.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: April 26, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Jie Chen
  • Non main CPU/OS based operational environment
    Patent number: 9305562
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Processor system and control method thereof
    Patent number: 9304943
    Abstract: A processor system according to the present invention includes a storage unit (10), a control information area (12) that stores an access prohibit flag (13) capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit (10) and a request for rewriting a copy register (32), a security PE that evaluates whether or not the request for rewriting the copy register (32) is valid, the copy register (32) that stores, when the access prohibit flag (13) is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag (13) is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit (21) that controls whether or not to allow access from the main PEa to the storage unit (10) based on an output value from the copy register (32).
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoaki Kanai
  • Read and write requests to partially cached files
    Patent number: 9298625
    Abstract: Aspects of the invention are provided to support partial file caching on a file system block boundary. All read requests are converted so that offset and count are aligned on a block boundary. Data associated with read requests is first satisfied from local cache, with cache misses supported with a call to persistent or remote system. Similarly, for a write request, any partial blocks are aligned to the block boundary. Data associated with the write request is performed on local cache and placed in a queue for replay to the persistent or remote system.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj P. Naik, Frank B. Schmuck, Renu Tewari
  • Multicore, multibank, fully concurrent coherence controller
    Patent number: 9298665
    Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Kai Chirca
  • Efficient processing of cache segment waiters
    Patent number: 9286227
    Abstract: For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks is initiated, and the at least one complete data track is removed off of a free list by a first I/O waiter.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Michael T. Benhase, Lokesh M. Gupta, David B. Whitworth
  • Sparse volume management cache mechanism system and method
    Patent number: 9286230
    Abstract: A method, computer program product, and computer system for instantiating, by a computing device, a slice-object associated with a slice when the slice-object is accessed. The slice-object is released to a slice object cache when accessing is complete. It is determined whether the slice is accessed within a threshold period of time. If the slice is accessed within the threshold period of time, the slice-object is retrieved from the slice-object cache. If the slice is not accessed within the threshold period of time, memory used for the slice-object is released.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 15, 2016
    Assignee: EMC Corporation
    Inventors: Ye Zhang, Jean-Pierre Bono, William C. Davenport, Yining Si, Qi Mao, Alexander M. Daniel
  • Apparatus and methods for communicating with programmable devices
    Patent number: 9274980
    Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: March 1, 2016
    Assignee: Altera Corporation
    Inventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
  • Expresscard adapter and electronic device
    Patent number: 9262358
    Abstract: An ExpressCard adapter able to accept a PCI-E-type or a USB-type ExpressCard in a single ExpressCard slot includes the ExpressCard slot, a PCI-E port, a data conversion unit, a switch unit, and a detection unit. The data conversion unit is connected to the PCI-E port, and converts between USB data and PCI-E data. The switch unit connects the ExpressCard slot to the PCI-E port or to the data conversion unit. The detection unit detects the type of ExpressCard which is inserted and controls the switch unit to connect the ExpressCard slot either to the PCI-E port or to the data conversion unit as required.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: February 16, 2016
    Assignee: ShenZhen Goldsun Network Intelligence Technology Co., Ltd.
    Inventors: Meng-Lin Tsai, Hsien-Chuan Liang
  • Split write operation for resistive memory cache
    Patent number: 9239788
    Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiangyu Dong, Xiaochun Zhu, Jungwon Suh
  • Apparatus for mixed signal interface circuitry and associated methods
    Patent number: 9236867
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 12, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Signal switching circuit and peripheral component interconnect express connector assembly having the signal switching circuit
    Patent number: 9235542
    Abstract: A signal switching circuit allows a PCIe card access to additional data channels when installation of the PCIe cards on first and second PCIe connectors are detected. First and second PCIe connectors output a first detection signal when each of the first and second PCIe connectors receives a PCIe card. The first and second PCIe connectors output a second detection signal when each of the first and second PCIe connectors does not receive a PCIe card. A first multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the first multiplexer, to transmit PCIe signals to the first or second PCIe connector. A second multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the second multiplexer, to transmit PCIe signals to the first or second PCIe connectors.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 12, 2016
    Assignee: Zhongshan Innocloud Intellectual Property Services Co., Ltd.
    Inventors: Lei Liu, Guo-Yi Chen
  • Variable-sized buffers mapped to hardware registers
    Patent number: 9223542
    Abstract: An interface includes a first hardware register field to store respective chunks of a command directed to a device and respective chunks of a response to the command from the device. The interface also includes a second hardware register field to store a size of the command and a size of the response. The first and second hardware register fields are accessible by the device and by a processor external to the device that generates the command, in response to memory not being available to buffer the command and the response.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: December 29, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Patryk Kaminski, Thomas R. Woller