Abstract: Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first logical partition in the communication fabric that includes a first processing device and a memory device, and directing transfer of configuration data for storage by the memory device over the first logical partition. After transfer of the configuration data, the method includes instructing the communication fabric to remove the first logical partition in the communication fabric, where the configuration data remains stored by the memory device after removal of the first logical partition. The method also includes instructing the communication fabric to establish a second logical partition in the communication fabric that includes at least a second processing device and the memory device comprising the configuration data, where the second processing device is operated using the configuration data.

Abstract: A signal processor is provided, the signal processor comprising a transaction buffer, a processing memory, a processing unit, and a bus connection that is configured to be connected to a bus system for data transmission, wherein the transaction buffer is configured to receive and save a set of data packets from the bus system, the data packets each comprise payload data and attributed address data, where the address data relate to an address of the processing memory, the processing memory is connected with the processing unit, the processing unit is configured to run a process routine, and the transaction buffer is configured to transfer payload data between the processing memory and the transaction buffer at a selectable instant of time during the process routine run by the processing unit. Furthermore, a method for transferring data is provided.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Abstract: A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register.

Abstract: A display control device includes a cancellation detection unit that is configured to detect a cancellation regarding a program rewrite from first update data stored in the rewrite target ECU to second update data acquired from an external device, a write instruction unit that is configured to distribute the second update data to the rewrite target ECU and instruct the rewrite target ECU to write the second update data thereinto, and a notification instruction unit that is configured to give an instruction for notification of a progress regarding the program rewrite. The notification instruction unit is further configured to give the instruction to make the notification of the progress regarding the program rewrite in a first manner when the write instruction unit is distributing the second update data, and give the instruction to make the notification of the progress regarding the program rewrite in a second manner when the cancellation detection unit detects the cancellation.

Abstract: A vector processor with a vector first and multi-lane configuration. A vector operation for a vector processor can include a single vector or multiple vectors as input. Multiple lanes for the input can be used to accelerate the operation in parallel. And, a vector first configuration can enhance the multiple lanes by reducing the number of elements accessed in the lanes to perform the operation in parallel.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Abstract: In some embodiments, a method can include receiving a signal representing a first status of a peripheral device. The method can further include identifying an action based on the first status of the peripheral device, each user from a subset of users being predesignated to perform the action. The method can further include sending, to a set of user devices, a signal representing the action. The method can further include receiving, from at least one user device, a signal representing an acceptance of the action. The method can further include sending, to each remaining user device from the set of user devices, a signal indicating the acceptance of the action by a different user device and a signal indicating that the action has been performed by the user and that causes the first status of the peripheral device to be changed to a second status of the peripheral device.

Abstract: A schema is generated to establish a connection between user devices and one or more patient record servers. Generating a schema can include receiving configuration information associated with a patient record gateway, wherein the patient record gateway is associated with one or more patient record servers configured for storing electronic health records for a plurality of patients. Generating a schema can include defining, based at least in part on the configuration information, a schema configured to enable user devices to retrieve, via the patient record gateway, electronic health records from the one or more patient record servers. A schema can be requested by a user device. The schema can be sent to a user device to establish a connection with the one or more patient record servers.

Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array.

Abstract: A scalable multi-stage hypercube-based interconnection network with deterministic communication between two or more processing elements (“PEs”) or processing cores (“PCs”) arranged in a 2D-grid using vertical and horizontal buses (i.e., each bus is one or more wires) is disclosed. In one embodiment the buses are connected in pyramid network configuration. At each PE, the interconnection network comprises one or more switches (“interconnect”) with each switch concurrently capable to send and receive packets from one PE to another PE through the bus connected between them. Each packet comprises data token, routing information such as source and destination addresses of PEs and other information. Each PE, in addition to interconnect, comprises a processor and/or memory. In one embodiment the processor is a Central Processing Unit (“CPU”) comprises functional units that perform such as additions, multiplications, or logical operations, for executing computer programs.

Abstract: A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.

Abstract: Disclosed are a solid-state microwave source and a branch consistency control method thereof. The branch consistency control method includes: collecting phase information of each branch unit under each of a plurality of preset target powers, and performing phase adjustment for each branch unit based on the phase information under each of the target powers; assembling coarsely-adjusted N branch units, a driver module, a power distribution module, a radial combiner, a circulator, and a waveguide coupler; adjusting a branch power by using the driver module and the power distribution module, to collect the phase information of each branch unit under each of the target powers; and when the phase information of each branch unit under each of the target powers meets a preset condition, performing phase adjustment for the branch unit based on the phase information.

Abstract: Enhanced techniques for communicating with an integrated circuit chip card are disclosed. An integrated circuit chip card may include a processor, a memory storing a plurality applications executable by the processor, an input/output (I/O) interface, and a network interface coupled to the (I/O) interface. The network interface may implement a plurality of logical ports, and the network interface can be configurable to select between multiple communication protocols to communicate with an external device in a socket communication mode. The network interface can be configured to establish a plurality of communication channels between the external device the integrated circuit chip card using the plurality of logical ports, and each of the communication channels may support communication with one of the plurality of applications.

Abstract: A method of generating executable instructions for a computing system is provided. The method comprises: receiving a first set of instructions including a kernel of a first operator and a kernel of a second operator, the kernel of the first operator including instructions of the first operator and write instructions to a virtual data node, the kernel of the second operator including instructions of the second operator and read instructions to the virtual data node; determining, based on a mapping between the write instructions and read instructions, instructions of data transfer operations between the first operator and the second operator; and generating a second set of instructions representing a fused operator of the first operator and the second operator, the second set of instructions including the instructions of the first operator, the instructions of the second operator, and the instructions of the data transfer operations.

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction in the same execution mode as the received instruction.