Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: Systems and methods for performance benchmarking-based selection of processor for generating graphic primitives. An example method comprises: initializing, by a computer system comprising a plurality of processors of a plurality of processor types, a current value of a graphic primitive parameter; for each processor type of the plurality of processor types, computing a corresponding value of a performance metric by generating, using at least one processor of a currently selected processor type, a corresponding graphic primitive of a specified graphic primitive type, wherein the graphic primitive is characterized by the current value of the graphic primitive parameter; and estimating, based on the computed performance metric values, a threshold value of the graphic primitive parameter.

Abstract: A server system, a method, and a non-transitory computer readable medium for hot plugging includes a CPLD detecting an existence of a NVME SDD in the server system, the CPLD transmitting a first signal to the NVME SDD, the NVME SDD starting to run; a BMC controlling a hot plug control module to run, the hot plug control module continuously outputting second signals and third signals; a logic selecting module receiving the first signal, the second signal, and the third signal, and selecting corresponding signals for outputting to the NVME SDD according to the third signal; and when the logic selecting module selecting the first signal and outputting the first signal to the NVME SDD, the NVME SDD keeping running; when the logic selecting module selecting the second signal and outputting the second signal to the NVME SDD, the NVME SDD executing hot plugging.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: The disclosed invention provides system and method for providing autonomous actions that are consistently applied to evolving missions in physical and virtual domains. The system includes a autonomy engine that is implanted in computing devices. The autonomy engine includes a sense component including one or more sensor drivers that are coupled to the one or more sensors, a model component including a world model, a decide component reacting to changes in the world model and generating a task based on the changes in the world model, and an act component receiving the task from the decide component and invoking actions based on the task. The sense component acquires data from the sensors and extracts knowledge from the acquired data. The model component receives the knowledge from the sense component, and creates or updates the world model based on the knowledge received from the sense component.

Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

Abstract: An electronic device includes a memory, a processor, and functional hardware. The memory includes a queue. The processor is configured to write a processing instruction into a target area of the queue. The functional hardware is configured to read the processing instruction from the target area and reserve the target area. The functional hardware generates a completion message according to the processing instruction, and writes the completion message into the target area after the processing instruction is executed. The completion message corresponds to the processing instruction.

Abstract: A method of synchronizing time between a host device and a storage device is provided. The method includes: identifying, by the storage device, a time synchronization interval; notifying the time synchronization interval from the storage device to the host device; providing host time information from the host device to the storage device during the time synchronization interval; and synchronizing, by the storage device, time information of the storage device with the host time information.

Abstract: A system and method for a virtual processor base/virtual execution context arrangement. The disclosed arrangement utilizes chiplets comprising core logic and defined instruction sets. The chiplets are adapted to operate in conjunction with one or more active execution contexts to enable the execution of particular processes. In particular, the defined instruction sets includes a instructions for processor debugging. The system and method support the compartmentalization of such debugging instructions so as to provide enhanced processor and process security.

Abstract: An online system trains a transformer architecture by an initialization method which allows the transformer architecture to be trained without normalization layers of learning rate warmup, resulting in significant improvements in computational efficiency for transformer architectures. Specifically, an attention block included in an encoder or a decoder of the transformer architecture generates the set of attention representations by applying a key matrix to the input key, a query matrix to the input query, a value matrix to the input value to generate an output, and applying an output matrix to the output to generate the set of attention representations. The initialization method may be performed by scaling the parameters of the value matrix and the output matrix with a factor that is inverse to a number of the set of encoders or a number of the set of decoders.

Abstract: Aspects of the disclosure relate to a dynamic event securitization and neural network analysis system. A dynamic event inspection and securitization computing platform comprising at least one processor, a communication interface, and memory storing computer-readable instructions may securitize event data prior to authorizing execution of the event. A neural network event analysis computing platform comprising at least one processor, a communication interface, and memory storing computer-readable instructions may utilize a plurality of event analysis modules, a neural network, and a decision engine to analyze the risk level values of data sharing events. The dynamic event inspection and securitization computing platform may interface with the neural network event analysis computing platform by generating data securitization flags that may be utilized by the neural network event analysis computing platform to modify event analysis results generated by the event analysis modules.

Abstract: The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.

Abstract: In various embodiments, a parallel processor includes a parallel processor module implemented within a first die and a memory system module implemented within a second die. The memory system module is coupled to the parallel processor module via an on-package link. The parallel processor module includes multiple processor cores and multiple cache memories. The memory system module includes a memory controller for accessing a DRAM. Advantageously, the performance of the parallel processor module can be effectively tailored for memory bandwidth demands that typify one or more application domains via the memory system module.

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: A multi-level signal receiver includes a data sampler having (M?1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M?1) reference voltages, to thereby generate (M?1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M?1) sense amplifiers by: (i) adjusting at least one of (M?1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M?1) reference voltages during a second training mode, based on equalized values of the (M?1) comparison signals, where each of the (M?1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

Abstract: A patient record gateway of an electronic health record system can be validated using a conformance statement that defines capabilities and characteristics of patient record servers associated with the gateway. Part of validating the patient record gateway includes performing a configuration test of the patient record gateway using the conformance statement.

Abstract: A method can include identifying a first key value of a first cell of a first grid of grids of cells to which a first feature maps, embedding the first grid into each cell of a second grid, identifying a second key value of a second cell of the second grid to which a second feature maps, the second key value representative of the first and second key values, comparing the identified key value to the key values of a memory, in response to determining the identified key value is in the memory, and providing data indicating a class associated with the identified key value in the memory.