Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C., thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.

Abstract: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Abstract: The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and second gate electrode region comprised of gate material doped with second ions for a second device. The respectively doped regions are connected by a silicide layer near the top surface of the gate conductors.

Abstract: A method of fabricating a dual panel-type active matrix organic electroluminescent device includes patterning a first metal layer to form a gate electrode, a gate line, a power line, a gate pad, and a power pad on a first substrate, forming a first insulating layer on the first substrate to cover the gate electrode, the gate pad, and the power pad, forming a semiconductor layer on the first insulating layer over the gate electrode, the semiconductor layer including an active layer of undoped amorphous silicon and an ohmic contact layer of doped amorphous silicon, forming source and drain electrodes, a data line, a first link electrode, and a data pad, wherein the source and drain electrodes are disposed on the ohmic contact layer, wherein the data line, the data pad, and the first link electrode are disposed on the first insulating layer, and wherein the first link electrode crosses the gate line, forming a channel within the active layer by etching a portion of the ohmic contact exposed between the source an

Abstract: To provide a semiconductor package mounting method, with excellent work efficiency, wherein the direction of a semiconductor package can be verified by a simple method before mounting. One corner of a square shaped display section provided on the surface of a semiconductor package body is chamfered such that the chamfer dimensions are different from those of the other corners. If image recognition by a camera determines that this chamfered part is located correctly, the orientation of a semiconductor package is determined to be correct. On the other hand, if image recognition determines that it is not located correctly, the orientation of the semiconductor package is adjusted until it is correct.

Abstract: There is provided a method of easily forming thin film transistors having the same characteristics in fabricating a differential circuit or a current mirror circuit utilizing two thin film transistors made of a polycrystalline silicon semiconductor. Four each thin film transistors are used in a differential circuit and a current mirror circuit, respectively. The thin film transistors are arranged to be symmetric to each other about a symmetry center instead of using thin film transistors arranged adjacently on the substrate in the respective circuits.

Abstract: An electronic component and a blank have plastic embedding compounds of a first and a second plastic layer. Semiconductor chips are embedded in the first plastic layer in such a way that their marginal sides are surrounded by a bead. The second plastic layer compensates for the unevenness of a upper boundary of the first plastic layer.

Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.

Abstract: A semiconductor substrate surface protection method for maintaining surfaces thereof clean includes providing a tank containing pure water and a chemical protection material which is a high molecular straight-chain organic compound; and immersing the semiconductor substrate in the tank to deposit the high molecular straight-chain organic compound on the semiconductor substrate for maintaining the surfaces thereof clean. This convenient method prevents deposition of contaminating substances directly onto the semiconductor substrate and enables maintaining of this contaminant-free surface at a low cost.

Abstract: In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. The present invention also relates to a memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within the array. Respective wordlines comprise a poly-metal stack formed over a semiconductor substrate in accordance with the present invention. Additionally, the present invention relates to a computer system comprising a memory cell array of the present invention.

Abstract: A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.

Abstract: An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

Abstract: A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode-field plate structure is disposed between the source and drain electrodes. The gate electrode-field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a second metal. The second metal has: a first portion disposed over and electrically connected to a portion of the first metal; and a second portion, separated from a second portion of the first metal by a portion of the dielectric and extending beyond an edge of the first metal to an edge of the second metal. The edge of the first metal is further from the drain electrode than the edge of the second metal to provide a field-plate for the field effect transistor.

Abstract: Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.

Abstract: A method of making a light active sheet. A bottom substrate having an electrically conductive surface is provided. A hotmelt adhesive sheet is provided. Light active semiconductor elements, such as LED die, are embedded in the hotmelt adhesive sheet. The LED die each have a top electrode and a bottom electrode. A top transparent substrate is provided having a transparent conductive layer. The hotmelt adhesive sheet with the embedded LED die is inserted between the electrically conductive surface and the transparent conductive layer to form a lamination. The lamination is run through a heated pressure roller system to melt the hotmelt adhesive sheet and electrically insulate and bind the top substrate to the bottom substrate.

Abstract: A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film formed on the surface of the semiconductor substrate and having a second silicide layer; and a silicon nitride film formed on the sidewall of the first gate electrode; a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film formed on the surface of the semiconductor substrate and having a fourth silicide layer thinner in thickness than the second silicide layer.

Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.

Abstract: A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.