Abstract: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed by depositing a silicon layer and an antireflective layer over the PMD layer. The silicon layer and the antireflective layer are etched to have holes with a regular taper. The holes through the PMD are anisotropically etched so as to have straight walls.

Abstract: A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the upper part of the upper line, and connects electrically to the second region of the lower line and the upper surface of the upper line. A lower interlayer insulating layer is interposed between the lower line and the upper line, and an upper interlayer insulating layer is interposed between the upper line and the fuse. The fuse is formed on the upper interlayer insulating layer. Both ends of the fuse connect electrically to the second region of the lower line and the upper line, respectively, through fuse holes penetrating the lower and upper interlayer insulating layers.

Abstract: We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.

Abstract: A method for manufacturing GaN LED devices is disclosed herein. First, a LED epitaxial layer is formed on a provisional substrate. Part of the LED epitaxial layer is removed to form a plurality of LED epitaxial areas. Then, a first transparent conductive layer, a metal reflective layer, and a first metal bonding layer are sequentially formed on the plurality of LED epitaxial areas and then part of the first transparent conductive layer, the metal reflective layer, and the first metal bonding layer are removed. Next, a permanent substrate is provided. At least a metal layer and a second metal bonding layer are formed on the permanent substrate. Then, part of at least the metal layer and the second metal bonding layer are removed. Next, the provisional substrate is bonded to the permanent substrate by aligned wafer bonding method. Then, the provisional substrate is removed to expose a surface of the LED epitaxial layer and then an n-type electrode is formed on the surface.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).

Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: A circuit carrier including a core layer, a passive component, a plurality of dielectric layers, and a plurality of circuit layers is provided. The core layer has a first surface and a second surface. In addition, the core layer has a hole, and the passive component is embedded in the hole of the core layer. Furthermore, the circuit layers and the dielectric layers are alternately disposed on the first surface and the second surface of the core layer respectively. The dielectric layers have a plurality of conductive vias, and at least one of the circuit layers is electrically connected to the passive component through the conductive vias. As described above, the electrical performance of the circuit carrier is enhanced. Furthermore, a manufacturing process of the circuit carrier mentioned above is also provided.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Abstract: A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A first passivation layer can be formed on at least portions of the mesa sidewalls and on the substrate adjacent the mesa sidewalls wherein at least a portion of the mesa surface is free of the first passivation layer and wherein the first passivation layer comprises a first material. A second passivation layer can be formed on the first passivation layer wherein at least a portion of the mesa surface is free of the second passivation layer, and wherein the second passivation layer comprises a second material different than the first material. Related devices are also discussed.

Abstract: A mounting method for a semiconductor component. The method includes application of solder material to the semiconductor component, application of at least one contact/mounting element made of semiconductor material and/or metal and/or insulator material to the solder material, heating of at least one part of the semiconductor component to a temperature lying above the melting point of the solder material by impressing an electrical power into the semiconductor component, as a result of which corresponding soldering connections arise between the semiconductor component and the at least one contact/mounting element, and cooling of the connection complex that comprises the semiconductor component and at least one contact/mounting element and was produced in the preceding step.

Abstract: This invention provides a manufacturing method for fabricating on the same substrate both high voltage thin film transistors suitable for driving liquid crystal and low voltage drive high performance thin film transistors. In addition, this invention provides a thin film transistor substrate where the area occupied by a storage capacitor in each pixel is reduced to raise the aperture ratio of the display unit. One aspect of this invention provides a manufacturing method characterized in that the impurity regions of both high voltage thin film transistors and high performance thin film transistors which differ in the thickness of gate insulation are formed by implanting a dopant through the same two-layered film. Another aspect of this invention reduces the area occupied by the drive circuit in the display unit by utilizing an extension of one layer of the insulation film included in each thin film transistor.

Abstract: Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a material having insulating properties. One or more of the plurality of cells can include a phase change material. The media is either grounded or electrically connected with a voltage source such that when the tip is placed in contact with the media and a voltage is applied to the tip, a current is drawn through the cell over which the tip is arranged. The current is drawn through the isolated cell at least a portion of the phase change material within the cell beneath the tip is heated to a sufficient temperature such that the material become amorphous in structure. The current is then removed from the phase change material, which is quickly cooled to form an amorphous domain having a resistance representing a “1” (or a “0”).

Abstract: A method for manufacturing a semiconductor device using a dual-damascene pattern, where a photosensitive film is coated instead of a dielectric material, the photosensitive film is cured, and the photosensitive film is entirely etched. The method includes forming a first conductor on a first insulation film deposited on a semiconductor substrate, and depositing second, third, and fourth insulation films on the first insulation. The method also includes forming holes by selectively removing the fourth and third films, forming a fifth insulation film where the holes are filled with the fifth film, and forming a sixth insulation film on the fifth and fourth films. The method further includes forming a trench mask pattern on the sixth film, forming trench line holes and trench via holes using the pattern and forming a barrier metal film and a second conductor, where the line and via holes are filled with the second conductor.

Abstract: An IC chip/substrate assembly bonded together by a non-conductive adhesive and a method for forming the assembly. The assembly consists of an IC chip that has bumps formed on an active surface, a substrate that has bond pads formed on a top surface, wherein at least one of the IC chip and the substrate has dummy bumps formed in-between the bumps or the bond pads, and a non-conductive adhesive disposed in between and bonding the IC chip and the substrate together in a face-to-face relationship with the bumps in electrical communication with the bond pads.

Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the structure. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of structure materials and oxidation methods.

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: A method of forming box-shaped cylindrical storage nodes includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a photoresist layer are then sequentially formed on the substrate. Using a first phase shift mask having line-and-space patterns, the photoresist layer is exposed, forming first exposure regions. Using a second phase shift mask having line-and-space patterns, the photoresist layer is exposed again, forming second exposure regions intersecting the first exposure regions. The photoresist layer is then developed, forming a photoresist pattern having rectangular-shaped openings formed at intersections of the first and the second exposure regions. The molding layer is etched using the photoresist pattern as an etch mask, forming storage node holes exposing the buried contact plugs. Storage nodes are formed inside the storage node holes.

Abstract: Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate structures are filled, and the polysilicon is drawn back to below the top edge of the fillings. The relief formed from the fillings and the polysilicon which has been caused to recede forms a shape which is used to pattern the gate metal without a lithographic step. The provision of a gate sacrificial layer, which is patterned together with the polysilicon layer, makes it possible to form contact structures from a contact metal prior to the application of the gate metal.

Abstract: Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.