Abstract: A serial communication system comprises: a master; a plurality of slaves; and a serial communication bus connecting the master and the plurality of slaves. The master is configured so as to perform peer-to-peer control, via the serial communication bus, of the plurality of slaves. Each of the plurality of slaves has: an I/O portion for controlling communication with the master; a control portion for controlling a driving portion of the slave; and a register portion. The register portion comprises a control program for the driving portion. The control program comprises a plurality of functions, and the register portion stores control information to which are allocated all or a portion of the plurality of functions corresponding to all or to a portion of the plurality of program steps.

Abstract: An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode.

Abstract: A computer capable of automatic bandwidth configuration according to I/O expansion card (e.g., PCI-Express expansion card) type is provided. A motherboard of the computer includes an I/O expansion slot, a chipset, and a configuration setting circuit. When the I/O expansion slot supports different types of I/O expansion cards having multiple interface card slot combinations, a corresponding bandwidth configuration message is generated on the I/O expansion card. The bandwidth configuration message is used to indicate the type of the I/O expansion card that is being used and thereby control the configuration setting circuit to adjust the bandwidth configuration in the chipset.

Abstract: A method for preventing deadlocks in a multiprocessing environment is provided. The method comprises receiving one or more strongly connected components (SCCs) as input, wherein a first SCC represents a set of locks such that each pair of locks in the set may potentially be involved in a deadlock situation; creating a first gate lock for the first SCC, wherein a first process or process element acquires the first gate lock before acquiring a first lock in the first SCC and releases the first gate lock after releasing a number of locks in the first SCC; and removing the first gate lock, in response to determining that the first gate lock introduces new deadlocks.

Abstract: A safety module (5) with terminals for connection to a bus system control module (2), which is provided for connecting input/output modules (4a, 4b) for field devices, via a databus (3), has a data processing unit (?C2), which is set up corresponding to the bus system control unit (2) for identical processing of the data transmitted via the databus (3). The data processing unit (?C2) for ensuring correct data communication with a safety function is set up in such a way that mutual checking of the safety function takes place by means of data exchange via the databus with the bus system control unit (2).

Abstract: A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.

Abstract: Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Abstract: According to one embodiment of the invention, a data modifying bus buffer generally includes a switch that is configured to selectively couple a first databus to a second databus. The switch is controlled by a buffer controller. The first databus and a second databus have a similar predetermined protocol. The buffer controller is operable to monitor the first databus for the presence of a particular sequence of the signals such that, when the particular sequence of the signals is found, the first switch may be selectively opened or closed.

Abstract: A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.

Abstract: An addressable SPI bus and an associated communication protocol. The addressable SPI bus comprises a plurality of slaves each exhibiting a particular address and a shift register whose output is connected to a common MISO bus by a buffer exhibiting a three state output, also known as a tri-state output. The master asserts a single SS line, which is connected in parallel to each of the plurality of slaves, indicating the beginning of a frame, and transmits via the MOSI bus the address of a particular slave of the plurality of slaves, denoted interchangeably the target or destination slave. Responsive to the received address, the target slave enables the three state output associated therewith thus transmitting the output of the target slave shift register to the master via the MISO bus.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to request service from a master device involve detecting a condition that asserts a request for service signal, at a common node independent from the serial data transfer bus, to a master device of the bus. The request for service is latched it, within the slave, such that the request for service remains asserted regardless of a change in the detected condition. The request for service is de-asserted in response to interrogation of the slave, using the serial data transfer bus, by the master device. Devices may be configured as general purpose Input/Output devices, CODEC arrangements, or other slave devices, and may conform to I2C and/or SMBus serial communication specifications.

Abstract: A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers in the second configuration.

Abstract: In a bus arbitration device that utilizes a resource use management device, upon detecting that a processor is permitted to access a memory, a detection unit decreases a counter by 1 and starts a timer, in a delay circuit, that is not in operation to count time. When the timer counts to a predetermined cycle time period, the delay circuit increases the counter by 1. A control unit permits the processor to access the memory, if the counter is larger than 0.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.

Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.

Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.