Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients.

Abstract: A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register.

Abstract: Aspects of the disclosure embody a multi-master two-wire serial bus that comprises two or more chained two-wire serial busses. The chained two-wire serial busses include a host two-wire serial bus with a first master device and one or more slave devices. One or more chained two-wire serial busses are coupled to the host bus wherein one or more slave devices on the host two-wire serial bus operate as second master devices, which comprise a digital state machine including a two-wire serial slave component coupled to the master device and a two-wire serial master component coupled to the slave devices on the chained two-wire serial bus. The digital state machine emulates a slave device on the host two-wire serial bus and a master device on the chained two-wire serial bus.

Abstract: In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device is ready to change from a first state to a second state in a specified duration. A negotiating procedure is performed to have the first link and the second link enter the second state simultaneously if the second link is detected to be in the first state within the specified duration.

Abstract: A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet.

Abstract: A data transfer control device including: a link controller which analyzes a packet received through a serial bus and generates a packet to be transmitted through the serial bus; an interface circuit which performs interface processing between the data transfer control device and a display driver connected to the data transfer control device through an interface bus; and a signal detection circuit which detects a vertical synchronization signal VCIN used for indicating a non-display period of a display panel and outputs a detection signal VDET. When the link controller has received a read request packet which requests reading of status of the VCIN, the link controller waits for the VDET to be output, and performs processing of transmitting a response packet through the serial bus on condition that the VDET has been output.

Abstract: Provided are a method, system, and program for initiating and using information used for a host, control unit, and logical device connections receiving a request to create a host port to control unit port connection. In a volume group data structure, a volume group entry is defined having a plurality of pointers for the host port and control unit port pair. At least one device address is added to the volume group that is accessible to the host port and control unit port connection by initializing at least one pointer in the volume group entry to address at least one device data structure. For each of the at least one device addresses, indication is made in the at least one device data structure addressed by the at least one pointer in the volume group entry that the device address is accessible to the host port and control unit port connection.

Abstract: Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A variety of signal processing algorithms can be implemented on the same application specific processor.

Abstract: A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event message. The interrupt handling system can also include a first resource operable to generate the first interrupt event message. In one form, the first interrupt event message can identify a first interrupt event occurrence detectable by the first system management interrupt handler. The interrupt handling system can further include a memory including a first allocated memory location configured to store the first interrupt event message using the first system management interrupt handler. In one form, the first system management interrupt handler can be responsive to a second system management interrupt handler request to read the first interrupt event message.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A system and method that allows a plurality of SR-PCIMs to operate within a PCIe fabric. The system and method describe a master SR-PCIM election process and transfer of mastership from a master SR-PCIM to a standby SR-PCIM under certain conditions. The system and method leverage the PCI configuration space and PCI messages so that SR-PCIMs from multiple vendors can potentially interoperate.

Abstract: A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.

Abstract: Techniques are provided for performing changes to a resource governed by a locking mechanism. An entity (such as a server instance in a database system cluster) requests permission to modify the resource. In response to the request, the entity receives a first lock on the resource, which grants permission to perform the change to the resource without making the change permanent. After receiving the first lock, the entity performs the change to a copy of the resource that resides in shared memory without making another copy of the resource. After performing the change and until receiving permission to make the change permanent, the entity prevents the change to the resource from becoming permanent. After performing the change, the entity receives a second lock on the resource, which grants the entity permission to make the change permanent. After receiving the second lock, the entity ceases to prevent the change to the resource from becoming permanent.

Abstract: A data transfer control device includes: a link controller which analyzes a packet received through a serial bus; an interface circuit which generates interface signals and outputs the interface signals to an interface bus; and a reset signal output circuit which outputs a reset signal to the interface circuit. The link controller analyzes a packet to determine whether or not the received packet includes synchronization signal generation direction information (synchronization signal code). The reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.

Abstract: An arrangement of a plurality of disk drives having a interconnect control card and a plurality of disk drive carriers. The interconnect control card includes a plurality of serial interconnects; each one of the serial interconnects comprising a plurality of serially connected switches. Each one of such disk drive carriers has thereon a different portion of the plurality disk drives. The disk drives on each one of the carriers are connected to the switches in a different one of the plurality of serial interconnects. The disk drives on different ones of the carriers provide a RAID group.

Abstract: Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data.

Abstract: Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.