Abstract: Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease surface recombination velocities, increase electronic efficiencies, or the like. In other embodiments, the organic passivating layer may be used as a protective sacrificial layer and reduce contact resistance or reduce resistance of doped regions. The organic passivation layer may be formed without the need for high-temperature processing.

Abstract: A semiconductor device using a TFT structure with high reliability is realized. As an insulating film used for the TFT, for example, a gate insulating film, a protecting film, an under film, an interlayer insulating film, or the like, a silicon nitride oxide film (SiNXBYOZ) containing boron is formed by a sputtering method. As a result, the internal stress of this film becomes ?5×1010 dyn/cm2 to 5×1010 dyn/cm2, preferably ?1010 dyn/cm2 to 1010 dyn/cm2, and the film has high thermal conductivity, so that it typically becomes possible to prevent deterioration due to heat generated at the time of an on operation of the TFT.

Abstract: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line.

Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.

Abstract: A method is disclosed for fabricating a silicon nitride regions in silicon carbide. The method includes the steps of implanting a sufficient dose and energy of nitrogen ions into a silicon carbide substrate maintained at a temperature above about 350° C. to produce an as-implanted layer of a silicon nitride composition in the silicon carbide, and annealing the as-implanted layer to form a silicon nitride composition. In some embodiments, the formed region of silicon nitride provides an insulating layer. In some embodiments, the silicon nitride region is buried under a surface layer of silicon carbide. Methods of separating silicon carbide by implantation and lift-off are additionally disclosed.

Abstract: Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device.

Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In one aspect of the present invention, an organosilicate glass film is exposed to an ultraviolet light source wherein the film after exposure has an at least 10% or greater improvement in its mechanical properties (i.e., material hardness and elastic modulus) compared to the as-deposited film.

Abstract: During the polishing of a semiconductor substrate, the semiconductor wafer that has been reduced in thickness, and hence in strength, by polishing, suffers outer-surface damage (or cracking) due to the initial damage caused by the use of polishing quartz. In order to solve these problems, the present invention applies a semiconductor substrate fixing jig formed with, on the face for fixing the semiconductor substrate, a groove(s) of almost the same diameter as that of the semiconductor substrate. Semiconductor substrate damage and cracking can be suppressed by applying this jig.

Abstract: A method for improving Mg doping of Group III-N materials grown by MOCVD preventing condensation in the gas phase or on reactor surfaces of adducts of magnesocene and ammonia by suitably heating reactor surfaces between the location of mixing of the magnesocene and ammonia reactants and the Group III-nitride surface whereon growth is to occur.

Abstract: A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.

Abstract: A selective polish for fabricating electronic devices is disclosed. The selective polish may include the use of a slurry that facilitates the selective polish of a first component but does not substantially polish a second component.

Abstract: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include aminosilane ligands.

Abstract: Method of preparing a silicon dioxide layer by high-temperature oxidation on a substrate of formula Si1-xGex in which x is greater than 0 and less than or equal to 1, the said method comprising the following successive steps: a) at least one additional layer of thickness hy and of overall formula Si1-yGey, in which y is greater than 0 and less than x, is deposited on the said substrate of formula Si1-xGex; and b) the high-temperature oxidation of the said additional layer of overall formula Si1-yGey is carried out, whereby the said additional layer is completely or partly converted into a layer of silicon oxide SiO2. Method of preparing an optical or electronic component, comprising at least one step for preparing an SiO2 layer using the method described above.

Abstract: A method for forming a shallow trench isolation layer that includes: forming a pad oxide on a substrate; forming a hard mask silicon nitride on the pad oxide; forming a moat pattern on the pad oxide and hard mask; etching partially the pad oxide and hard mask with the moat pattern to open the silicon nitride; and ashing process for removing the moat pattern.

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.

Abstract: Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

Abstract: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.

Abstract: A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the seed layer. The dummy gate defines a location for the gate conductor. Semiconductor devices having a dummy gate plated thereon to a width of between about 10 to about 70 nanometers are also provided.