Abstract: A process and system for processing a thin film sample (e.g., a semiconductor thin film), as well as the thin film structure are provided. In particular, a beam generator can be controlled to emit at least one beam pulse. With this beam pulse, at least one portion of the film sample is irradiated with sufficient intensity to fully melt such section of the sample throughout its thickness, and the beam pulse having a predetermined shape. This portion of the film sample is allowed to resolidify, and the re-solidified at least one portion is composed of a first area and a second area. Upon the re-solidification thereof, the first area includes large grains, and the second area has a region formed through nucleation. The first area surrounds the second area and has a grain structure which is different from a grain structure of the second area. The second area is configured to facilitate thereon an active region of an electronic device.

Abstract: A manufacturing method of a thin film transistor of a liquid crystal display device using 3-mask includes forming a gate electrode over a substrate, consecutively forming a gate insulating layer and an active layer, forming a first photoresist pattern, removing an active layer formed at a source/drain region, ashing the first photoresist pattern to expose a part of an active region, forming a source/drain electrode, forming a passivation layer, forming a second photoresist pattern that exposes a pixel region over the passivation layer; forming a pixel region by using the second photoresist pattern as a mask, side-etching a part of the passivation layer to expose a part of the drain electrode, forming a pixel electrode material over the second photoresist pattern and the pixel region, and simultaneously removing the second photoresist pattern and the pixel electrode material formed thereon to form a pixel electrode.

Abstract: An electronic device containing a polythiophene wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n represents the number of repeating monomer segments in the polymer or the degree of polymerization.

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.

Abstract: One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form a plurality of hemispherical microcavities in the silicon dioxide. Openings in the patterned nitride are filled, then another layer is formed over the silicon nitride layer using the silicon nitride as a support over the microcavities. An inventive structure resulting from the method is also described.

Abstract: Embodiments of the current invention describe ammonia hydroxide treatments for surfaces. In one embodiment, a method and a cleaning solution including ammonium hydroxide (NH4OH), water (H2O), a chelating agent, and a surfactant for cleaning silicon germanium substrates are described. The cleaning solution does not include hydrogen peroxide (H2O2) because hydrogen peroxide etches germanium. In another embodiment, a method of terminating oxidized surfaces on semiconductor substrates with terminating groups that promote the bonding of the oxidized surface to another surface with a surface treatment containing ammonium hydroxide (NH4OH) is described. The oxidized surface is immediately bonded to a second substrate after evaporation of the surface treatment.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.

Abstract: Silicon nanocrystals with chemically accessible surfaces are produced in solution in high yield. Silicon tetrahalide such as silicon tetrachloride (SiCl4) can be reduced in organic solvents, such as 1,2-dimethoxyethane(glyme), with soluble reducing agents, such as sodium naphthalenide, to give halide-terminated (e.g., chloride-terminated) silicon nanocrystals, which can then be easily functionalized with alkyl lithium, Grignard or other reagents to give easily processed silicon nanocrystals with an air and moisture stable surface. The synthesis can be used to prepare alkyl-terminated nanocrystals at ambient temperature and pressure in high yield. The two-step process allows a wide range of surface functionality.

Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: Zinc-oxide nanostructures are formed by forming a pattern on a surface of a substrate. A catalyst metal, such as nickel, is formed on the surface of the substrate. Growth of at least one zinc oxide nanostructure is induced on the catalyst metal substantially over the pattern on the surface of the substrate based on a vapor-liquid-solid technique. In one exemplary embodiment, inducing the growth of at least one zinc-oxide nanostructure induces growth of each zinc-oxide nanostructure substantially over a patterned polysilicon layer. In another exemplary embodiment, when growth of at least one zinc-oxide nanostructure is induced, each zinc-oxide nanostructure grows substantially over an etched silicon substrate layer.

Abstract: Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.

Abstract: A receiving layer is formed from a thermosetting resin precursor. An interconnecting layer is formed on the receiving layer from a dispersion liquid containing conductive particles. Heat is applied to the receiving layer and the interconnecting layer to cure the thermosetting resin precursor and to bond the conductive particles together.

Abstract: A semiconductor material which has a high carbon dopant concentration and is composed of gallium, indium, arsenic and nitrogen is disclosed. The material is useful in forming the base layer of gallium arsenide based heterojunction bipolar transistors because it can be lattice matched to gallium arsenide by controlling the concentration of indium and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentration obtained.

Abstract: In a method of forming contact holes without using a vacuum device, a resist film at positions corresponding to contact hole forming regions above a source region 16, a drain region 18 and a gate electrode 34 of a polysilicon film 14, is exposed and developed to form mask pillars 40. Then a liquid insulating material is applied onto the whole surface of a glass substrate 10 except for the mask pillars 40, to form an insulating layer 42. Next the mask pillars 40 are removed by ashing, and an insulating layer 42, second contact holes 44 and first contact holes 28 which pass through a gate insulating film 26 are formed.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.

Abstract: The present invention is generally directed to electroluminescent Ir(III) compounds, the substituted 2-phenylpyridines, phenylpyrimidines, and phenylquinolines that are used to make the Ir(III) compounds, and devices that are made with the Ir(III) compounds.