Abstract: To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.

Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

Abstract: A power supply ECU is configured to carry out extreme value search control for searching for a frequency at which a detected value of power loss is minimized, by oscillating a frequency of output power from an inverter. Then, the power supply ECU determines whether or not extreme value search in extreme value search control is poorly proceeding, and when extreme value search is poorly proceeding, the power supply ECU increases an amplitude of frequency oscillation of output power from the inverter.

Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

Abstract: An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT?, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM?. The load elements are not coupled directly to the output terminals OUT+ and OUT?, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM?, enabling a modular approach where multiple instances of the multiplexer may be combined on an “as-needed” basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

Abstract: The present application discloses a driving device for a power device, which includes a control circuitry configured to receive at least a system switching command and a feedback signal of a power device, and to generate a pull-up strength control signal or a pull-down strength control signal according to the received signals; and a pull-up array and/or a pull-down array, coupled between the control circuitry and the power device, and configured to provide a corresponding pull-up or pull-down strength for the power device according to the pull-up or pull-down strength control signal. The present application also discloses the corresponding electric appliance and power device driving method.

Abstract: In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor. The RDAC is further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA), and a non-inverting input connected to the output port of the first transistor.

Abstract: This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.

Abstract: In a delay control circuit having a plurality of series-coupled delay stages, an input signal is routed through one of the series-coupled delay stages via a first delay element if a first delay control value is in a first state, the first delay element imposing a first signal propagation delay according to a first bias signal. If the delay control value is in a second state, the input signal is routed through the one of the series-coupled delay stages via a second delay element instead of the first delay element, the second delay element imposing a second signal propagation delay according to a second bias signal. The first and second bias signals are calibrated such that the second signal propagation delay exceeds the first propagation delay by a predetermined time interval that is substantially briefer than the first signal propagation delay.

Abstract: An electronic apparatus is provided which includes switching elements, resonance suppression resistors which have first ends connected to control terminals of the switching elements and second ends having a common connection, an on-drive circuit which has an on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements, and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements. A resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors. The off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: The invention concerns a frequency locked loop comprising: a digitally controlled oscillator (102) configured to generate a frequency signal (F); a frequency counter (310) configured to generate an estimate (f_EST) of the frequency of the frequency signal based on a reference clock signal (CLK_REF); and a controller (314) configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the estimated frequency, wherein the controller is clocked by a further clock signal (CLK) having a variable frequency, and the controller is configured to generate a trigger signal (AUTO_CLEAR) for triggering a counting phase of the frequency counter.

Abstract: The present disclosure provides a method and a device for simulation of a CMOS radio frequency switch and a communication terminal. The method includes: receiving a first value; obtaining a current value of a first function based on the first value, when the CMOS radio frequency switch is in an on-state, the value of the first function is a first function value, and when the CMOS radio frequency switch is in an off-state, the value of the first function is a second function value; receiving a second value; receiving a third value; outputting an off-state capacitance value of the CMOS radio frequency switch based on the second value and the third value; and outputting an on-state resistance value of the CMOS radio frequency switch based on the second value, the third value and the current value of the first function.

Abstract: In described examples, a first power switching circuit receives a power switching control signal and activates a first power switch in response to the power switching control signal. A second power switching circuit receives the power switching control, activates a second power switch in response to the power switching control signal, and determines a first power switching delay in response to temperature indications of the first and second power switches. The second power switching circuit activates the second power switch at a first delayed time after the activation of the first power switch, where the first delayed time follows the activation of the first power switch by the determined first power switching delay.

Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.

Abstract: A high efficiency converter is provided. The converter can be used in applications requiring fast transient response under a first loading condition, and high efficiency under a second loading condition. The converter converts one or more input voltages via two or more conversion paths. Each of the two or more conversion paths corresponds to a different loading condition which indicates a magnitude of a load driven by the converter (e.g., heavy or light), and a target transient response of the load (e.g., fast or slow). A conversion path for a heavy or fast loading condition converts an input voltage directly to a target output voltage. A conversion path for a light or slow loading condition includes a two-stage architecture.

Abstract: The present disclosure describes a composite device including first field effect transistor (FET) device and second FET device. First FET device includes first drain, first source, first gate and shielding terminal. First FET device is made of wide-bandgap semiconductor material. Second FET device includes second drain, second source, and second gate. First and second FET devices are electrically connected in cascode configuration for providing a capacitive path between drain and gate terminals of composite device such that current flowing through gate terminal controls slew rate of drain voltage appearing at drain terminal. Cascode configuration includes an electrical connection of first drain to drain terminal, an electrical connection of first source to second drain, an electrical connection of second gate to first gate and gate terminal, an electrical connection of shielding terminal to second source, and an electrical connection of second source to source terminal of composite device.

Abstract: A switching power supply can include multiple power MOSFETs that receive an initial gate drive waveform comprising a fast slew rate region having a negative slope and a slow slew rate region also having a negative slope. The MOSFETs can turn off during the slow slew rate region of the initial gate drive waveform.

Abstract: A semiconductor device that compensates for imbalance between a plurality of semiconductor elements connected in parallel by negative feedback to achieve current balance utilizing reversed temperature characteristics without providing any dedicated element just for cancelling temperature characteristics. A gate driving circuit turns ON a power semiconductor element by applying a voltage elevated by a charge pump (CP) circuit to a gate through a resistor connected between the CP circuit and the gate. The power semiconductor element is turned OFF by control circuit that gives a control signal to turn ON a MOS switch in the gate driving circuit and discharges the gate through a diode.

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.