Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

Abstract: A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.

Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first circuit that includes a level shift transistor, a transmission line through which the signal output from the first circuit propagates, a second circuit that is connected the transmission line to receive the signal propagating through the transmission line, and a third circuit that is connected to the transmission line. The first circuit is connected to a power supply line to which a first voltage is supplied, and outputs, to the transmission line, a signal having an amplitude lower than the first voltage by a threshold voltage of the level shift transistor. The third circuit allows a current to flow from the transmission line when a voltage of the transmission line exceeds a set voltage.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Abstract: Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal.

Abstract: A semiconductor memory device includes: memory units arranged in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the memory units; first gate electrodes arranged in the first direction and opposed to the first semiconductor layers; a first wiring extending in the first direction and connected to the first semiconductor layers; second wirings arranged in the first direction, and connected to the first gate electrodes; second semiconductor layers arranged in the first direction and disposed at first end portions of the second wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; third semiconductor layers arranged in the first direction and disposed at second end portions of the second wirings; and third gate electrodes arranged in the first direction and opposed to the third semiconductor layers.

Abstract: Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

Abstract: Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

Abstract: A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse.

Abstract: A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.