Abstract: In an exclusive lock management in common to both the In-Band and the Out-of-band, a lock control technique of a storage system capable of removing the factor that may cause the discrepancy in the configuration information in a disk array system is disclosed. In the storage system, a shared memory in a DKC of a storage subsystem has lock management information for uniformly managing the operation authority for the configuration information in the shared memory that is used in common by both the channels of the host terminals and the management client terminals, and a CPU in the DKC gives the operation authority for changing the configuration information to either the host machine or the management client based on the lock management information in the shared memory in response to an access request from the host terminals or the management client terminals.

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

Abstract: A disk array system where a plurality of SATA drive enclosures are connected through an FC loop is made capable of continuing to process data even in the event of a fault. When the system is normally operated, a first system controller and a second system controller execute read/write operations from and to disks of a SATA drive enclosure of a disk array via a first interface connector and a second interface connector, respectively, through the FC loop. When an error occurs on a second backend FC loop, the second system controller disconnects itself from the failed second backend FC loop and switches the path to a first backend FC loop which is normally functioning, to access the disk drive.

Abstract: A storage system capable of cutting back the resource while obtaining a WORM function. A controller (110) functions to: obtain, when a write request is made by a computer (300), information on one of logical devices that is a target of a write process, from a memory module (140); and inform, when the logical device is set to unwritable, a signal indicating that the logical device is set to unwritable, to the computer (300). An interface (200) functions to: reference meta-information held in a disk drive (130) to obtain a list of files that are not accessed for a predetermined period; secure a logical device; and cause the controller (110) to store, the files on the list of files and set the logical device that stores the files in a manner that makes information stored in the memory module (140) unwritable.

Abstract: A computer 10a stores boot information OA1 and application information AP1 stored on a local disk 16a, the information being respectively stored as an OS1 shared file group in a shared LU1 and as a AP1 shared file group in a shared LUn+1. For personal information (including personal information of boot information or AP information), computer 10a stores the information as a user personal file group in an personal LU1. Computer 10a transmits image outline information, LU information and file information for the sets of information stored in shared LU1, shared LUn+1 and personal LU1 to an disk-image management server 30, where the information is stored in the storage device 31 of the disk-image management server 30.

Abstract: Provided are an area management table, an operation management policy, and a resource broker. In the area management table, one or more physical area IDs for identifying one or more storage area candidates selected from a plurality of physical storage areas, are associated with each application program. The operation management policy states a guideline for storage area assignments based on operational status of each server provided with the application programs. The resource broker detects the operational status of each server, and based on the detected operational statuses and the operation management policy, determines physical storage areas to assign to each application program.

Abstract: A method of controlling a computer having a plurality of memory buses adapted to be operated in a multi-channel mode by reading memory information of at, least one of a plurality of memory modules connected to the respective memory buses and displaying whether the plurality of the memory buses can operate and/or are operating in the multi-channel mode by comparing the read memory information. Thus, a user can confirm whether a plurality of memory buses operate in a multi-channel mode.

Abstract: Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

Abstract: A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.

Abstract: A storage unit which purges unnecessary data immediately and transfers data with high probability of future hits from a disk medium to a segment buffer in advance. A section calculates feature values of data to be stored in a new generated segment and relationships between preceding and succeeding commands. Next, a section retains the feature values for a predetermined period after segment data is purged from a segment buffer and stores the feature values of the purged segment as feature values of a segment with a high hit probability after the purge, when an address stored by the purged segment is read again. Then, a section does not purge a segment when the segment has feature values similar to those of the segment having a high hit probability, while purging another segment or other plural segments with a different feature value.

Abstract: Various embodiments of a multiprocessing computer system employing capacity prefetching are disclosed. In one embodiment, a cache subsystem implements a method for prefetching data. The method includes the cache subsystem receiving a request for data, and determining a cause of a cache miss that occurs in response to the request. The cache subsystem includes a controller that selectively prefetches additional data depending upon the cause of the cache miss. In one embodiment, determining the cause of the cache miss includes determining whether a cache line corresponding to the request exists in the cache memory of the cache subsystem in an invalid state. Additional data is prefetched in response to determining that the cache line is not present in the cache memory in an invalid state.

Abstract: When destinations of memory devices constituting one virtual volume increase, a relay device performs data transfer among plural memory devices such that a structure of the virtual volume can be changed so as to reduce the destinations of the memory devices as much as possible with this increase in the destinations as an opportunity for data transfer. In addition, when memory areas with a relatively small capacity increase among unused memory areas in which a virtual volume is not constituted, the relay device performs data transfer among the plural memory devices such that the number of the memory areas with a small capacity is reduced as much as possible with this increase in the memory areas as an opportunity for data transfer.

Abstract: A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

Abstract: Provided are a method, system, and program for encoding data onto a storage medium. Host data is received and a plurality of device blocks are generated to include the host data. A directory is generated including entries for physical locations on the storage medium, wherein each entry identifies one device block at the physical location corresponding to the entry, and wherein the directory is used to access data on the storage medium. The directory entries are encoded in the device blocks written to the storage medium.

Abstract: An interleaving method and apparatus provides parallel access in a linear and interleaved order to a predetermined number of stored data samples. A memory array with a plurality of memory devices is addressed by applying a first portion of an address to memory devices and by using a second portion of the address to select at least one memory device to be accessed, wherein the position of the first and second portions within the address is changed in response to a change between the linear order and the interleaved order. Due to the fact that the memory array is split into several individually addressable memory devices, each of these memory devices can be accessed in a linear and interleaved order by changing an allocation of a chip selection portion and a chip addressing portion of the address.

Abstract: Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.

Abstract: A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: This invention relates to a micro-system for burn-in system program from a backup memory of plug-able subsystem into main memory and method thereof, wherein data codes via the data bus accessed by processor from the backup memory or the main memory are determined by two devices for adjusting level.

Abstract: In at least some embodiments, a system comprises a computer configured to boot using at least one of a plurality of boot techniques involving tape media. The system further comprises a tape drive coupled to the computer and a tape that is readable by the tape drive, wherein the tape is formatted to support a plurality of different boot techniques and wherein at least one of the supported boot techniques is compatible with the computer.