Patents Examined by Craig E Walter
  • Patent number: 7100015
    Abstract: One embodiment of the present invention provides a system that facilitates redirecting external memory allocation operations, generated during calls by an application to external library functions, to an internal memory manager within the application. The system starts by encountering a call to an external library function during execution of the application. The system then determines if the external library function can call an internal memory allocation function, and if so, redirects the call to an internal memory allocation function within the application.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 29, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Bernd J. W. Mathiske, Teck Yang Lee
  • Patent number: 7096337
    Abstract: In one embodiment of the invention, a disk storage accessing system for enabling a plurality of computers to share and access a plurality of disk storages comprises a plurality of computers that refer to the disk storages. Each of the computers includes a counting module for counting a frequency of accesses to each of the disk storages, and a module for receiving an access path change command to change access paths for the computer to access a different disk storage according to the command. The system further comprises an instructing module for collecting and totaling a frequency of accesses to each disk storage, and for instructing the receiving module of a computer that accesses the copy source disk storage after receiving a report of copy completion, to change access paths so as to access a target disk storage instead of the copy source disk storage.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yagi, Motoaki Hirabayashi
  • Patent number: 7096338
    Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices are combined. The volumes belonging to storage devices A–D are managed virtually integrally. A host recognizes a plurality of storage devices A–D as a single virtual storage device. The user is able to group the volumes belonging to the storage system, as a plurality of storage layers 1–3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes to be moved V1 and V2, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Toru Takahashi, Tatsundo Aoshima, Nobuo Beniyama, Takaki Kuroda
  • Patent number: 7093102
    Abstract: Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector gather and scatter operations. By contrast, one embodiment of the present invention implements gather and scatter operations using a plurality of deposit and extract instructions. As a result, gather and scatter operations may be efficiently performed within a general purpose processing environment and without the need for dedicated gather/scatter hardware.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventor: Carole Dulong
  • Patent number: 7085882
    Abstract: Disclosed herein are an SRAM-compatible memory and method of driving the SRAM-compatible memory. The SRAM-compatible memory has memory banks, a parity generator and a parity bank. The memory banks each store corresponding one of input data in its DRAM cells specified by an input address. The memory banks perform write operations independently such that when a refresh operation or a write operation for a previous frame is being performed with respect to DRAM cells of a certain memory bank, the write operation of the input data is independently performed with respect to the respective memory banks except for the certain memory bank. The parity generator generates a input parity determined based on the input data and a certain preset parity value. The parity bank stores the input parity.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: August 1, 2006
    Assignee: Silicon7 Inc.
    Inventors: Sun Hyoung Lee, In Sun Yoo, Dong Woo Shin
  • Patent number: 7085899
    Abstract: An efficient snapshot technique based on a mapping for a large logical volume shared in multiple hosts. According to the present invention, problems of time delays in a conventional snapshot technique is solved by employing a FAB and an SSB, which are bits representing whether a COW operation is carried out to a mapping entry. In other words, the present invention solves the problems of delaying a write operation of corresponding volume, which is simultaneously executed when a snapshot is created, until the snapshot creation is completed.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 1, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Ho Kim, Dong Jae Kang, Yu Hyeon Bak, Chang Soo Kim, Bum Joo Shin, Myung Joon Kim
  • Patent number: 7082509
    Abstract: A method and system for allocating memory during system boot to reduce operating system memory resource consumption at run-time. A memory heap comprising a portion of a computer system memory in which a first class of firmware components are to be loaded is allocated. Firmware components are then selectively loaded into the system memory during system boot operations, wherein firmware components corresponding to the first class are loaded into the memory heap, while other firmware components are loaded into other portions of the system memory. A memory map corresponding to the physical memory configuration at the completion of system boot is then handed off to an operating system, which provides a virtual mapping of the physical memory such that the first class of firmware components may be accessed at run-time via virtual address calls. In one embodiment the first class of firmware components comprise run-time services.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: July 25, 2006
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Michael A. Rothman
  • Patent number: 7080220
    Abstract: A method, apparatus, processor, system, and signal-bearing medium that in an embodiment determine which page to replace in memory when the memory is full based on reference and re-reference indicators in page table entries. In an embodiment, a reference indicator in an entry is set when its associated page is accessed in memory and the reference indicator was previously clear. The re-reference indicator in an entry is set when its associated page is accessed and the reference indicator was previously set. Both the reference and re-reference indicators are cleared if their associated page is accessed and both were previously set. When a new page is accessed and the memory is full, a page in the memory is not available for replacement if both its reference and its re-reference indicators are set. Otherwise, the page is available for replacement.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Dirk Michel
  • Patent number: 7076620
    Abstract: A data processing system includes a first storage system including a first host and a first storage subsystem. The first host has access to a first copy manager that is operable to manage a data replication operation. A second storage system includes a second host and a second storage subsystem. The second host has access to a second copy manager that is operable to manage a data replication operation. A first communication link is coupled to the first storage system and the second storage system to exchange management information between the first and second storage systems in order to manage the data replication operation. A data transfer path is configured to transfer data stored in the first storage subsystem to the second storage subsystem and replicate the data of the first storage subsystem in the second storage subsystem. The data transfer path is different from the first communication link.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: July 11, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Takeda, Yoshihiro Asaka, Kenji Yamagami, Katsuyoshi Suzuki, Tetsuya Shirogane
  • Patent number: 7073013
    Abstract: A memory device includes a first, directly executable memory with boot code, a second memory with operating system code, and a common connector. When the device is connected to a computer that lacks a BIOS of its own, the computer boots from the first memory and downloads the operating system from the second memory. A user of a system that includes a plurality of the memory devices and a computer that lacks a BIOS selects an operating system by reversibly connecting the appropriate memory device to the computer. The memory device also serves as a security key for a computer that lacks a BIOS.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: July 4, 2006
    Assignee: H-Systems Flash Disk Pioneers Ltd.
    Inventor: Menahem Lasser
  • Patent number: 7065613
    Abstract: The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: June 20, 2006
    Assignee: Maxtor Corporation
    Inventors: Lance Flake, Andrew Vogan
  • Patent number: 7058781
    Abstract: During a collection interval, if a multi-threaded generational, copying garbage collector finds that a card contains a reference to a younger generation, it gives a corresponding card table entry a youngergen value selected from a plurality of youngergen values at the beginning of the interval as the “current” youngergen value. The youngergen value chosen for a given collection interval differs from the one that was chosen for the previous collection interval. As a result, a collector thread is able to distinguish between a card in which a reference to the younger generation remained at the end of the previous interval and one identified by some other thread during the current interval as referring to a young-generation object. In that way, the thread is able to avoid unnecessary scanning.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: June 6, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: David L. Detlefs
  • Patent number: 7055005
    Abstract: A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The RAM controller may store such data into a prefetch buffer.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: May 30, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: William J. Walker, Andy Olsen
  • Patent number: 7051162
    Abstract: A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The memory controller may store such data into a prefetch buffer.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: May 23, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Hahn Vo
  • Patent number: 7047358
    Abstract: This invention describes a high-performance, log-structured implementation of a RAID subsystem that can be efficiently implemented in software. The methods described here allow the RAID subsystem to achieve high performance without using specialized hardware such as non-volatile memory or hardware XOR/DMA engines. Furthermore, the RAID implementation described here is well suited for supporting many functions required for advanced storage virtualization such as virtual disks, graceful addition and removal of disks, tolerating multi-disk failures, and snapshots.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: May 16, 2006
    Assignees: Boon Storage Technologies, Inc., Middlefield Ventures, Inc., Synapse Fund II, LLC, Nike Partners, L.P.
    Inventors: Edward K. Lee, Boon-Lock Yeo
  • Patent number: 7047367
    Abstract: An information processing device is provided which is capable of automatically initializing external apparatuses, when external apparatuses are connected thereto. A storage area for storing information identifying the type of external device connected to the information processing device and information identifying the characteristics of the external device is provided, and the external device connected is determined provisionally from information relating to the characteristics of an external device stored in the storage area, in cases where an external device of a type which is not present in the information processing device is detected.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: May 16, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yuko Nabekura, Yoshinori Igarashi, Tomoyuki Kato, Koichi Hori
  • Patent number: 7047368
    Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: May 16, 2006
    Assignee: SiRF Technology, Inc.
    Inventors: Nicolas P. Vantalon, Steven A. Gronemeyer, Vojislav Protic
  • Patent number: 7047389
    Abstract: The present invention provides a memory allocation method and the like, meaning that user usability and the level of service for the user can be improved. The present invention is a method for allocating memory to an application, wherein in cases where, upon receiving a memory acquisition request, the required size cannot be acquired even by executing memory recovery processing, a judgment is made of whether or not a generated memory shortage state is temporary on the basis of memory recovery information relating to past memory recovery processing, and the required size requested; when the memory shortage state is judged to be temporary, in principle, rather than immediately performing error processing, an attempt is made to acquire memory by performing memory recovery processing once again after a predicted wait time determined on the basis of the memory recovery information and the required size has elapsed.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 16, 2006
    Assignee: Fujitsu Limited
    Inventor: Masayuki Maeda
  • Patent number: 6996667
    Abstract: If a disk drive receives a program transfer command issued by a host system, a program specified by the command is written to a disk. Next time the disk drive is powered on, a process is executed during an activating process, the process including using the program written to the disk to rewrite a program stored in a nonvolatile memory.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: February 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Aoki, Yasumasa Nakano