Abstract: A signal processing device includes a distributing unit and a plurality of correcting units with different processing performance, the distributing unit distributes a bit sequence having a first number of bits to the first correcting unit, and a bit sequence having a second number of bits less than the first number of bits to the second correcting unit having lower processing performance than the first correcting unit, the first correcting unit applies error correction processing to the bit sequence having the first number of bits distributed to the first correcting unit, and the second correcting unit applies error correction processing to the bit sequence having the second number of bits distributed to the second correcting unit.

Abstract: An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16k mode or a 64k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.

Abstract: Provided are a transmission method, apparatus and system and a computer-readable storage medium. The transmission method includes creating an automatic repeat request process for a first packet; setting a lifetime for the automatic repeat request process; and sending the first packet. The lifetime is set for the automatic repeat request process so that the automatic repeat request process can be removed in time. In this manner, in the case where a limited number of automatic repeat request processes are simultaneously supported, a new automatic repeat request process can be created for a newly transmitted packet in time, and thus the transmission efficiency is improved.

Abstract: Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.

Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.

Abstract: According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques.

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Abstract: An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.

Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.

Abstract: An apparatus and method for a base station (BS) in a cellular network for uplink (UL) Joint Reception of Coordinated Multi Point (JR-CoMP) operations, wherein the User Equipment (UE) sends to the serving and coordinating Radio Units (RUs) a first data block, wherein because of different channel qualities, first data block arriving as second data block at serving RU and as third data block at coordinating RU, respectively. The Baseband Unit (BBU) associated with these RUs using two nested HARQ processes: First, a ‘fake’ HARQ process to combine the separately channel processed second data block with the third data block; then, a real HARQ process to combine the fake HARQ-combined data block with the retransmitted first data block. Fake HARQ uses Chase Combining while real HARQ uses Incremental-Redundancy Combining.

Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: The present technology relates to a memory system and a method of operating the same. The memory system includes a memory device including a plurality of semiconductor memories, and a controller configured to control the memory device to select a victim block based on a fail bit number of some data, among data that is programmed in each of the plurality of semiconductor memories, corresponding to a specific program state, and configured to perform a garbage collection operation on the selected victim blocks.

Abstract: Techniques for establishing a network connection via a physical medium after exiting a low-power state. The technique includes receiving circuit configuration information for configuring a circuit for establishing a network connection via a physical medium. The technique also includes determining first redundancy information based on the circuit configuration information. The technique also includes storing the determined first redundancy information and the circuit configuration information. The technique also includes entering, by the circuit, a low-power state, and exiting the low-power state. The technique also includes determining second redundancy information based on the stored circuit configuration information after the circuit has exited the low-power state. The technique also includes comparing the second redundancy information to the first redundancy information. The technique also includes detecting an error based on the comparing.

Abstract: A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

Abstract: There is provided a decoding circuit including; a first decoding unit that decodes a first signal from a multiplexed signal in which the first signal and a second signal are multiplexed in an LDM (Layered Division Multiplexing) system; and a second decoding unit that decodes the second signal from the multiplexed signal using the decoding result of the decoded first signal, wherein the second signal is selectively decoded based on noise information related to a reception state of the multiplexed signal.