Abstract: The present disclosure provides a semiconductor test method. The semiconductor test method includes the operations of: receiving a source code written in an interpreted language; and performing, by a first test apparatus, a first test on a device under test (DUT) based on the source code. The operation of performing, by the first test apparatus, the first test on the DUT based on the source code includes the operations of: interpreting, by a processor, the source code to generate a first interpreted code; and performing the first test on the DUT according to the first interpreted code. The first test apparatus is configured to execute the first interpreted code written in a first language.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A semiconductor device includes a plurality of first micro-bumps suitable for transferring normal signals; a plurality of a second micro-bumps suitable for transferring test signals; and a test circuit including a plurality of scan cells respectively corresponding to the first and second micro-bumps. The test circuit is suitable for applying signals stored in the respective scan cells to the first and second micro-bumps, feeding back the applied signals from the first and second micro-bumps to the respective scan cells, and sequentially outputting the signals stored in the scan cells to a test output pad.

Abstract: A temporal jitter analyzer analyzes temporal jitter and includes: a time delay controller; a time delay member; a delay measurement circuit; an edge generator in communication with the time delay member and that receives the delayed primary signal from the time delay member and produces a reference signal from the delayed primary signal; a decision circuit in communication with the edge generator and that: receives the reference signal from the edge generator; receives a detector signal; and produces a raw decision signal from the detector signal such that a value of the raw decision signal depends on the reference signal; and a decision circuit readout in communication with the edge generator and the decision circuit and that: receives the reference signal from the edge generator; receives the raw decision signal from the decision circuit; and produces a decision signal from the raw decision signal based on the reference signal.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

Abstract: It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

Abstract: A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: One embodiment provides a memory module that enables online repair of defective memory cells. The memory module includes a memory array storing data, a self-test controller coupled to the memory array and configured to perform a self-test on a region within the memory array without interrupting operations of the memory module, and a memory-repair module configured to repair a defective memory cell identified by the self-test controller.

Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure relates to encoding and decoding by using a polar code in a wireless communication system, and an operation method of a transmission-end apparatus includes determining segmentation and the number of segments, based on parameters associated with encoding of information bits, encoding the information bits according to the number of check bits, and transmitting the encoded information bits to a reception-end apparatus.

Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.

Abstract: In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

Abstract: Aspects of the subject disclosure may include, for example, obtaining a received channel-encoded data block having information bits, a transmitted error-check value, and redundant code bits. The redundant code bits correspond to a channel code applied to the received channel-encoded data block prior to transmission via a communication channel. A channel code type is identified and responsive to it being systematic, the information bits and the transmitted error-check value are obtained without decoding according to the channel code. The received channel-encoded data block is checked according to the transmitted error-check value to obtain a result. Responsive to the result not indicating an error, extracting the information bits without decoding the received channel-encoded data block according to the channel code. Responsive to the result indicating an error, decoding the received channel-encoded data block according to the channel code to obtain decoded information bits. Other embodiments are disclosed.

Abstract: A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.

Abstract: A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: Systems and methods for intelligent packet repetition in mobile satellite service links to overcome channel blockages. One example method includes transmitting and receiving packetized wireless communications between first and second communications devices via a bidirectional wireless link. The method includes receiving, by a first communications device from a second communications device, feedback information including an indication of a blockage in the communication channel, the indication including information indicating the presence and extent of the blockage, wherein the feedback does not include status indications for individual received packets. The method includes, responsive to receiving the indication of a blockage in the communication channel, determining a packet repeat value based on the feedback information, wherein the packet repeat value is greater than one.

Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.