Abstract: According to this invention a plurality of kinds of circuit blocks is formed as a circuit block area on a chip substrate to have a desired logic function. An array of signal output wires and array of signal input wires are formed adjacent the circuit block area such that these arrays intersect each other. First switching elements are each formed at a corresponding intersection of the signal output wire and signal input wire. An LSI device having a desired logic function can be implemented by electrically and fixedly writing an ON or OFF state of the first switching element. A first control wire and second control wire are provided adjacent to the circuit block area with the wire arranged parallel to the signal output wire and the wire arranged parallel to the signal input wire. Second switching elements are arranged at intersections of the first control wire and the signal input wires and at intersections of the second control wire and signal output wires.

Abstract: Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.

Abstract: An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.

Abstract: An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.

Abstract: A sensing amplifier for a random access memory (RAM) having a first differential amplifying circuit formed of a first pair of transistors having their sources connected together, their gates supplied with differential input signals, and their drains connected with symmetrical type active loads; and a second differential amplifying circuit of a current mirror type formed of a pair of transistors which is connected in series with the first differential amplifying circuit.

Abstract: A single, programmable, multifunctional input circuit scheme for integrated circuit chips is disclosed. An input pin is provided with selectable input logic circuit blocks, each capable of providing an input signal to another circuit in the integrated circuit system architecture. The user of the chip is provided with means for programming said pin to select one of said logic circuit blocks, whereby each said pin has multifunction capability.

Abstract: An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line.

Abstract: An ordinary differential type gate circuit has two transistors to which complementary inputs are given and which are turned on and off, and complementary type outputs in accordance with the states of the complementary inputs are generated from the collectors of those transistors. In this invention, there are further added a fixed threshold type gate circuit to which is inputted a control signal and a circuit which, when the control signal is inputted to this fixed threshold type gate circuit, generates complementary outputs in constant states irrespective of the states of the complementary inputs in response to the state of the control signal, thereby preventing the inputs applied to the differential type gate circuit from being reflected to the outputs.

Abstract: A CMOS input level shifting circuit includes a temperature-compensating N-channel field effect transistor structure wherein a resistance in series with the source region includes an extension of a lightly doped P-type region in which the source and drain regions are diffused. This structure produces a temperature-compensating variation in the drain current proportional to the square of the series resistance without requiring modification of standard processes for manufacturing CMOS integrated circuits. The relatively large, temperature-dependent variation of the series resistance produces a corresponding temperature-dependent variation in the drain current that effectively temperature-compensates the switching point of the CMOS input level shifting circuit.

Abstract: A power-up reset circuit for providing a reset signal for resetting circuit elements such as flip-flops upon the application of power to the circuit includes a CMOS pair output section and a capacitor coupled to the gates of the CMOS transistors. The capacitor is charged up by the power supply to switch the reset signal to a low level after the resetting operation has been achieved. In order to accommodate slow ramping power supplies, circuitry operating as a voltage sensitive switch is included to prevent the capacitor from charging until the power supply voltage has reached a sufficient level to ensure proper operation. In order to accommodate fast ramping power supplies, the charging rate of the capacitor is controlled to assure a minimum necessary duration of the reset signal.

Abstract: An integrated circuit has an identifying circuit coupled to an input. The input has ESD protection. The identifying circuit has a fuse which is in one of two possible states to provide the identifying information. A power on reset circuit provides a pulse in response to application of power to the integrated circuit. A current path between a power supply terminal and the input is provided in response to the power on reset pulse when the fuse is in one state. This current path is blocked when the fuse is in the other state. A user is thus provided with identifying information by the presence or absence of a current path at the input at the time when power is applied.

Abstract: A device for controlling the states of various parts of a main circuit during "power-on" operations which includes an auxiliary circuit for generating a disabling signal when the value of the main circuit supply voltage is below a threshold value for use in disabling the parts of the main circuit.

Abstract: A CMOS sense amplifier is disclosed which has the capacitance of the bit lines isolated from the sensing nodes, which allows the sensed differential voltage to be amplified faster than in current CMOS sense amplifiers, since the sensing nodes have significantly lower capacitance than the bit lines. The isolation is achieved by connecting the bit lines to only the gates of the upper transistors of the cross-coupled inverters, and by coupling the gates of the lower transistors to the common nodes of the inverters (i.e., the sensing nodes of the sense amplifier). In this way, the bit line voltages causes the cross-coupled inverters to begin switching based on the upper transistor of the inverter coupled to the bit line with the lower voltage being more conductive than the upper transistor of the other inverter; the cross-coupled arrangement of the lower transistor gates to the sensing nodes causes the required amplification and latching action.

Abstract: A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.

Abstract: The voltage gain of an MOS transistor inverter stage is made independent of the device threshold voltages and of channel lengths by making the length and width of the channel region of the upper load transistor equal to the length and width of the channel region of the lower driver transistor.

Abstract: A CMOS charged pump circuit for biasing the N well of a memory array. The present invention utilizes a multivibrator oscillator coupled to a constant current source to provide a frequency output which is independent of the supply voltage. The multivibrator oscillator uses less power than prior art ring oscillators. Feedback through a comparator circuit is used to monitor the N well voltage so that the multivibrator oscillator and ultimately the charge pump may be duty cycled to further reduce power consumption.

Abstract: At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaranteed to be low at the end of the precharging phase as is desired for inputs to all domino logic.

Abstract: Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.

Abstract: Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.

Abstract: A three-state output buffer delivering digital signals to a multi-line bus when in the data state, and presenting a high-impedance to the bus in the third state. The buffer output includes a two-transistor totem pole. Individual control transistor drivers are provided to switch the output transistors off when switching to the third state. The control transistors are actively driven both on and off. One of the output transistors includes an inverted-mode auxiliary collector which reduces base drive and saturation in that transistor, and which serves to hold off the other output transistor. Common control circuitry for all the buffer stages includes special means for reducing saturation effects to speed up control signals.