Abstract: There are provided a method for producing a photovoltaic element with stabilised efficiency, and a device which may be used to carry out the method, for example in the form of a specially adapted continuous furnace. A silicon substrate to be provided with an emitter layer and electrical contacts is thereby subjected to a stabilisation treatment step. In that step, hydrogen, for example from a hydrogenated silicon nitride layer, is introduced into the silicon substrate, for example within a zone (2) of maximum temperature. The silicon substrate may then purposively be cooled rapidly in a zone (3) in order to avoid hydrogen effusion. The silicon substrate may then purposively be maintained, for example in a zone (4), within a temperature range of from 230° C. to 450° C. for a period of, for example, at least 10 seconds. The previously introduced hydrogen may thereby assume an advantageous bond state.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a redistribution layer (RDL); disposing an etch stop layer over a RDL; patterning the dielectric layer and the etch stop layer; disposing a first seed layer over the etch stop layer and a portion of the dielectric layer that is exposed through the etch stop layer; disposing a second patterned photoresist over the first seed layer; disposing a conductive material over a portion of the first seed layer that is exposed through the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material that protrudes from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.

Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures.

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Abstract: A method of forming a structure having a coating layer includes the following steps: providing a substrate; coating a fluid on the surface of the substrate, where the fluid includes a carrier and a plurality of silicon-containing nanoparticles; and performing a heating process to remove the carrier and convert the silicon-containing nanoparticles into a silicon-containing layer, a silicide layer, or a stack layer including the silicide layer and the silicon-containing layer.

Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.

Abstract: A method for manufacturing a semiconductor device is provided. In the method, first substrate is prepared. Each of the first substrates has first product regions. The first substrates are stacked, thereby electrically connecting different layers of the first substrates via a through-electrode. A second substrates having second product regions is prepared. Second semiconductor chips are attached to the second product regions. The second semiconductor chips are attached to the second substrate on a top layer of the first substrates. The second substrate is removed from the second semiconductor chips. First electrode pads of the top layer are electrically connected to second electrode pads of the second semiconductor chips via through-electrodes. The second semiconductor chips are connected to each other in parallel. The first and second product regions are separated, thereby manufacturing semiconductor chip stacks including more semiconductor chips in the top layer than the other layers.

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid including at least one second transistor, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

Abstract: A method of fabricating a semiconductor may include forming on a substrate a mold structure including a mold layer, a buffer layer, and a support layer, performing on the mold structure an anisotropic etching process to form a plurality of through holes in the mold structure, and forming a plurality of bottom electrodes in the through holes. The buffer layer has a nitrogen content amount that increases as approaching the support layer from the mold layer. The buffer layer has an oxygen content amount that increases as approaching the mold layer from the support layer.

Abstract: A display device including a display panel having a first surface and a second surface opposite to the first surface, a guide structure disposed on the first surface of the display panel, and a window disposed on the second surface of the display panel, in which the guide structure includes a guide film configured to apply a preliminary pressure to the display panel, and a cover panel disposed between the guide film and the display panel, the cover panel including a cushion layer.

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.