Abstract: A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 ?m. The substrate satisfies that a ratio of ??/? is not more than 0.1, where ? is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and ?? is a difference (???L) between the thermal expansion coefficient ? and a thermal expansion coefficient ?L calculated from a temperature change in lattice constant of the substrate.

Abstract: This document discloses an organic light emitting device comprising a first electrode and a wire comprising a contact part formed on a substrate, an insulating layer formed on the first electrode and a portion of the wire, the insulating layer comprising an opening which exposes a portion of the first electrode and a contact hole which exposes an entire upper surface of the contact part, an emission layer formed in the opening, a second electrode formed on the emission layer and the upper surface of the contact part though the contact hole.

Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

Abstract: A semiconductor topography and a method for forming a drain extended metal oxide semiconductor (DEMOS) transistor is provided. The semiconductor topography includes at least a portion of an extended drain contact region formed within a well region and a plurality of dielectrically spaced extension regions interposed between the well region and a channel region underlying a gate structure of the topography. The channel region of a first conductivity type and the well region of a second conductivity type opposite of the first conductivity type. In addition, the plurality of dielectrically spaced extension regions and the extended drain contact region are of the second conductivity type. Each of the plurality of dielectrically spaced extension regions has a lower net concentration of electrically active impurities than the well region. Moreover, the extended drain contact region has a greater net concentration of electrically active impurities than the well region.

Abstract: A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

Abstract: An electronic device includes a base having a first wiring thereon; a flexible film having a second wiring thereon; a plurality of elements each including a first connecting portion and a second connecting portion; and an adhesive agent layer, wherein each of the elements is sandwiched between the base and the film in a state in which the first connecting portion is in contact with the first wiring, the second connecting portion is in contact with the second wiring, and a tensile force is applied to the film, and, in this state, the base and the film are bonded with the adhesive agent layer.

Abstract: A solid-state imaging apparatus is provided. The solid-state imaging apparatus includes a solid-state imaging device, an ?-ray shielding layer formed so as to cover at least an imaging area of the solid-state imaging device and a cover glass provided above the ?-ray shielding layer.

Abstract: An integrated circuit includes a vertical diode defined by crossed line lithography.

Abstract: Disclosed is a light emitting diode structure including a Constructive Oxide Contact Structure contact layer. The light emitting diode structure comprises a substrate, a buffer layer formed on the substrate, a lower confinement layer formed on the buffer layer, a light emitting layer formed on the lower confinement layer, an upper confinement layer formed on the light emitting layer, a Constructive Oxide Contact Structure contact layer formed on the upper confinement layer whose conducting type can be P-type, N-type, or I-type, a first electrode, and a second electrode (transparent electrode). The transparent electrode is formed on the Constructive Oxide Contact Structure contact layer as an anode of the light emitting diode. The first electrode is formed on the lower confinement layer and is spaced apart from the light emitting layer, the upper confinement layer, the contact layer, and the transparent electrode. The first electrode is used as a cathode of the light emitting diode.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.

Abstract: A group III nitride compound semiconductor light-emitting device according to the present invention includes: an active layer (105) comprised of a group III nitride compound semiconductor; a current blocking layer (108) which is formed on the active layer (105) and has a striped aperture (108a); a superlattice layer (p-type layer 109) which buries the aperture (108a) and is comprised of a group III nitride compound semiconductor including Al; and a cladding layer (110) which is formed on the superlattice layer and is comprised of a group III nitride compound semiconductor including Al. When an average Al composition ratio of the superlattice layer is represented as x1 and an average Al composition ratio of the cladding layer (110) is represented as x2, it is represented as x1<x2.

Abstract: A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer.

Abstract: An LED illumination device can include a bridge connection circuit that includes five LED chips. The LED chips can be installed such that four LED chips, through which half-wave rectified current flows, are disposed in a generally cross-shaped opposed arrangement with the remaining LED chip interposed therebetween. The remaining LED chip can also have a full-wave rectified current flowing therethrough. Half-wave rectified currents having phases shifted by 180° (half the period) can flow through respective LED chips installed at a generally right angle. The placement range for the five LED chips can be limited, and the LED chips can be sealed with a wavelength conversion material.

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract: The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Abstract: In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

Abstract: A heterojunction bipolar transistor (HBT) has a (In)(Al)GaAsSb/InGaAs base-collector structure. A discontinuous base-collector conduction band forms a built-in electric field to infuse electrons into a collector structure effectively, while a discontinuous base-collector valence band prevents holes from spreading into the collector structure at the same time. Thus, a current density is increased. In addition, the small offset voltage of the base-emitter and base-collector junctions reduce a power consumption.

Abstract: A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.

Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.