Abstract: A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.

Abstract: The invention provides a side-view LED having an LED window opened to a side to emit light sideward. A pair of lead frames each act as a terminal. An LED chip is attached to a portion of the lead frame and electrically connected thereto. A package body houses the lead frames and has a concave formed around the LED chip. Also, a high reflective metal layer is formed integrally on a wall of the concave. A transparent encapsulant is filled in the concave to encapsulate the LED chip, while forming the LED window. In addition, an insulating layer is formed on a predetermined area of the lead frames so that the lead frames are insulated from the high reflective metal layer. The side-view LED of the invention enhances light efficiency and heat release efficiency with an improved side-wall reflection structure.

Abstract: A nitride-based semiconductor LED comprises an anode; a first p-type clad layer having a second n-type clad layer coming in contact with the anode, the first p-type clad layer being formed under the anode such that a portion of the first p-type clad layer comes in contact with the anode; an active layer formed under the first p-type clad layer; a first n-type clad layer having a second p-type clad layer which does not come in contact with the active layer, the first n-type clad layer being formed on the entire lower surface of the active layer; and a cathode formed under the first n-type clad layer and the second p-type clad layer so as to come in contact with a portion of the first n-type clad layer and the second p-type clad layer.

Abstract: A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.

Abstract: A liquid crystal display device including gate wiring or a gate electrode formed on a substrate on a TFT side of the TFT liquid crystal display device, wherein the wiring or the electrode has a structure of being held between two different insulation layers or insulators, and the structure is comprised of a first layer mainly consisting of copper and a second layer consisting of an oxide covering an outer circumferential part of the first layer, further, the second layer has compositional formula of CuxMnySizO (0<X<Y, 0<Z<Y).

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate having an operation layer on the top surface thereof; a source electrode and a drain electrode disposed on the operation layer; a gate electrode disposed between the source electrode and the drain electrode; and a field plate electrode disposed on an insulating film deposited between the gate electrode and the drain electrode. At least a part of the gate electrode is disposed in a gate recess formed in the operation layer, the field plate electrode is apart from the gate electrode by a predetermined distance, and at least a part of the field plate electrode is disposed in a field plate recess formed in the operation layer.