Abstract: A laser dicing method includes: placing a workpiece substrate on a stage; generating a clock signal; emitting a pulse laser beam synchronous with the clock signal; switching irradiation and non-irradiation of the workpiece substrate with the pulse laser beam in a unit of light pulse in synchronization with the clock signal to perform first irradiation of the pulse laser beam on a first straight line by controlling the pulse laser beam using a pulse picker; performing second irradiation of the pulse laser beam on a second straight line, which is adjacent to the first straight line in a substantially parallel fashion, after the first irradiation; and forming a crack reaching a workpiece substrate surface on the workpiece substrate by the first irradiation and the second irradiation.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.

Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract: A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.

Abstract: According to one embodiment, a method for patterning a medium having a patterned hard mask applied thereon is disclosed herein. The patterned hard mark includes a plurality of apertures exposing portions of the medium. The method includes directing ions toward the medium, implanting a portion of the ions into the exposed portions of the medium, removing a layer of the patterned hard mask with another portion of the ions, and depositing hard mask material onto the patterned hard mask. Depositing hard mask material onto the exposed portions of the medium may follow implantation of the portion of the ions into the exposed portions of the medium.

Abstract: A method of producing a transistor includes providing a substrate including an electrically conductive material layer stack positioned on the substrate. A first electrically insulating material layer is deposited so that the first electrically insulating material layer contacts a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally deposited so that the second electrically insulating material contacts the first electrically insulating layer, and contacts a second portion of the electrically conductive material layer stack, and contacts at least a portion of the substrate.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.

Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.

Abstract: A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.

Abstract: A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 300 C and about 400 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. A partial selenization is performed at a temperature between about 300 C and about 400 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 400 C and about 550 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.

Abstract: A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.

Abstract: Approaches are provided for forming a semiconductor device (e.g., a FET) having a multi-function layer (e.g., niobium carbide (NbC)) that serves as a work function layer and a gate metal layer in gate stacks of solid state applications. By introducing a single layer with multiple functions, total number of layers that needs processing (e.g., recessing) may be decreased. As such, the complexity of device integration and resulting complications may be reduced.

Abstract: A method for manufacturing an LED module includes following steps: providing a SMT (Surface Mount Technology) apparatus having a CCD (Charge-Coupled Device) image sensor and a nozzle, and providing a PCB and fixing the PCB in the SMT apparatus; providing a plurality of LEDs and mounting the LEDs on the PCB by the SMT apparatus; providing a plurality of lenses each having a plurality of patterned portions formed on an outer face of the lens, and the CCD image sensor imaging the lens and identifying the patterned portions, and then the SMT apparatus obtaining a location of the lens relative to the LED; positioning the lens on the PCB to cover the LED by the SMT apparatus; and fixing the lens on the PCB.

Abstract: The invention is directed to a surface emitting semiconductor light-emitting diode (LED) in which a reflector layer (4) of the first conductivity type is provided between a substrate (2) and a first barrier layer (5). A first contact layer (9) has at least one emitting surface (13) via which radiation emitted by an active layer (6) exits the LED. The emitting surfaces (13) are electrically and optically isolated from one another by surface implanted regions (11) in the first contact layer (9) which are irradiated with electric charge carriers. The areas of the layers located below the emitting surface (13) starting from the first contact layer (9) and proceeding as far as at least through the active layer (6) are electrically and optically isolated with respect to areas of the layers not located below the emitting surface (13) by means of first deep implanted regions (12.1) irradiated with electric charge carriers.

Abstract: The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates.

Abstract: Embodiments of the present invention relate to reducing the size variation on a wafer fabrication. In some embodiments, at least a portion the backfill material over features larger than a threshold size is etched or milled to provide backfill protrusions over those features. The backfill protrusions are configured to reduce the size variation across the fabrication. Embodiments of the invention may be used in fabrication of many types of devices, such as tapered wave guides (TWG), near-field transducers (NFT), MEMS devices, EAMR optical devices, optical structures, bio-optical devices, micro-fluidic devices, and magnetic writers.