Patents Examined by Dan D Le
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Patent number: 7624500Abstract: The disclosure relates to circuits and methods for the manufacture of circuits, such as those which avoid the formation of undesirable short circuit paths. One such method maintains a layout area of a fluid composition receiving layer within a layout area of a dielectric layer. Another such method relates to the application of fluid composition receiving layers, conductive layers, and dielectric layers, such as in the provision of printed circuits.Type: GrantFiled: August 15, 2007Date of Patent: December 1, 2009Assignee: Lexmark International, Inc.Inventors: Xiaorong Cai, Michael John Dixon, Yimin Guan, Elios Klemo, Bryan Dale McKinley, Paul Sacoto, Jeanne Marie Saldanha Singh, George Nelson Woolcott, Frank Edward Anderson
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Patent number: 7617599Abstract: Methods of packaging systems pressure-sensitive devices that are subject to human contact force are disclosed. The methods include coupling and attaching the sensing devices and at least one other integrated circuit to a substrate; applying and curing a relatively-soft, protective material over the sensing portion of the sensing device; positioning a covering tool over the cured material; applying and curing a relatively-hard, protective coating around the covering tool and the relatively-soft, protective material; and applying a second, relatively-soft, protective material in the void left by the withdrawn covering tool.Type: GrantFiled: December 5, 2007Date of Patent: November 17, 2009Assignee: Memsic, Inc.Inventors: Zongya Li, Matthieu Lagouge, Hongyuan Yang, Yanwei Chen
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Patent number: 7614146Abstract: The present invention provides a circuit board structure and a method of fabricating circuit board structure the same, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.Type: GrantFiled: October 4, 2007Date of Patent: November 10, 2009Assignee: Phoenix Precision Technology CorporationInventor: Shih-Ping Hsu
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Patent number: 7603762Abstract: An optical lapping guide for determining an amount of lapping performed on a row of sliders in a process for manufacturing sliders for magnetic data recording. The optical lapping guide is constructed with a front edge that is at an angle with respect to an air bearing surface plane ABS plane, such that a portion of the lapping guides is in front of the ABS and portion of the lapping guide is behind the ABS. As lapping progresses, an increasing amount of the lapping guide will be exposed at the ABS and visible for inspection. Therefore, after a lapping process has been performed, the optical lapping guide can be inspected to determine the amount of material removed by lapping. The greater the amount of the lapping guide that is exposed and visible, the greater the amount of material removed by lapping.Type: GrantFiled: December 15, 2006Date of Patent: October 20, 2009Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Amanda Baer, Vladimir Nikitin, Aron Pentek, Neil Leslie Robertson
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Patent number: 7600315Abstract: This invention relates to a method of manufacturing a printed circuit board, in which a dummy metal frame enclosing the outer periphery of a product part is formed, thus simultaneously assuring the rigidity of the printed circuit board and minimizing the warping thereof thanks to the dummy metal frame left in place on a finished product, thereby realizing a structure compatible with conventional flip chip mounting lines.Type: GrantFiled: December 31, 2007Date of Patent: October 13, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Takayuki Haze
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Patent number: 7596863Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.Type: GrantFiled: January 12, 2007Date of Patent: October 6, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: Ashwinkumar C. Bhatt, Robert J. Harendza, Robert M. Japp
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Patent number: 7596864Abstract: A method for soldering a soft wire to a printed circuit board conveniently includes the following step: providing a bracket having a through hole and an enameled wire; fastening the enameled wire to the bracket with the conductive wire crossing over the through hole; providing a printed circuit board formed with conductive pads thereon and setting the printed circuit board onto the bracket with the pad aligned to the through hole so that a portion of the magnet wire crossing the through hole lies on the conductive pad; providing a soldering tool having a thermal contact portion and inserting the thermal contact portion into the through hole to solder the magnet wire to the conductive pad.Type: GrantFiled: March 15, 2007Date of Patent: October 6, 2009Assignee: Hon Hai Precision Ind. Co., Ltd.Inventors: John Chow, Huan Chen, Chih-Min Lin
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Patent number: 7594318Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.Type: GrantFiled: September 12, 2007Date of Patent: September 29, 2009Assignee: Motorola, Inc.Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
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Patent number: 7591067Abstract: A thermally enhanced coreless thin substrate with embedded chips, which mainly includes a patterned carrier metal layer, at least one chip, at least one dielectric layer and at least one wiring layer, is disclosed. The chip is attached to a heat sink portion of the patterned carrier metal layer. The dielectric layer is formed over the patterned carrier metal layer and covers the chip. The wiring layer is formed on the dielectric layer for electrically connecting the patterned carrier metal layer and the chip. In the process of manufacturing the thermally enhanced coreless thin substrate with embedded chips, the heat sink portion is formed by patterning the patterned carrier metal layer after finishing the formation of the wiring layer. Thus, a thin board type electronic device that combines a heat sink, a carrier substrate and embedded chips together to form an integral unit is fabricated.Type: GrantFiled: December 27, 2006Date of Patent: September 22, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventor: Chien-Hao Wang
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Patent number: 7587815Abstract: A resin-coated metal plate used as a protective plate in drilling a printed wiring board has a metal plate and a resin film including a thermoplastic resin coated on at least one surface of the metal plate. A melting peak temperature of the thermoplastic resin is in a range of 60-120° C., and in a TMA curve, a temperature difference exhibited by the thermoplastic resin is within a range of 5° C. to 30° C. in a period while penetration of the probe is changed from 10% to 100% of the resin thickness in a temperature range of 20° C. to 200° C.Type: GrantFiled: July 25, 2007Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Eiichiro Yoshikawa, Akitoshi Fujisawa
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Patent number: 7581312Abstract: A method for manufacturing a multilayer FPCB includes the steps of: providing a first copper clad laminate, a second copper clad laminate and a binder layer; defining an opening on the binder layer; defining a first slit on the first copper clad laminate; laminating the first copper clad laminate, the binder layer and the second copper clad laminate; defining a via hole for establishing electric connection between the first copper clad laminate and the second copper clad laminate; cutting the first copper clad laminate, the binder layer and the second copper clad laminate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.Type: GrantFiled: October 23, 2007Date of Patent: September 1, 2009Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Foxconn Advanced Technology Inc.Inventors: Chih-Yi Tu, Cheng-Hsien Lin, Ming Wang
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Patent number: 7530157Abstract: A method of manufacturing coils that includes forming a predetermined number of U-shaped conductor segments. The U-shaped conductor segments are twisted using first twisting formation jig composed of a first inside ring and a first outside ring and a second twisting formation jig composed of a second inside ring and a second outside ring. The U-shaped conductor segments that are twist formed in radially inward directions are radially compressed. The U-shaped conductor segments are twist formed by holding one of each pair of straight portions by holding slots that are circumferentially formed in each of a first and second inside rings and first and second outside rings. Next, first and second inside rings and the first and second outside rings are coaxially rotated.Type: GrantFiled: August 2, 2007Date of Patent: May 12, 2009Assignee: Denso CorporationInventor: Yukinori Sawada
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Patent number: 7526846Abstract: Microelectromechanical systems with structures having piezoelectric actuators are described. The structures each have a body that supports piezoelectric islands. The piezoelectric islands have a first surface and a second opposite surface. The piezoelectric islands can be formed, in part, by forming cuts into a thick layer of piezoelectric material, attaching the cut piezoelectric layer to a body having etched features and grinding the piezoelectric layer to a thickness that is less than the depths of the cuts. Conductive material can be formed on the piezoelectric layer to form electrodes.Type: GrantFiled: September 6, 2007Date of Patent: May 5, 2009Assignee: FUJIFILM Dimatix, Inc.Inventors: Andreas Bibl, John A. Higginson