Abstract: A semiconductor integrated circuit device with the SOI structure is provided, which decreases the chip area of wiring lines interconnecting p- and n-channel IGFETs, raising their integration level. This device is comprised of a semiconductor layer formed on an insulating substrate. The semiconductor layer has a first area extending along a first direction and a second area extending along the first direction. The first and second areas are adjacent to one another. A first IGFET of a first conductivity type is formed in the first area of the semiconductor layer. A second IGFET of a second conductivity type opposite to the first conductivity type is formed in the first area of the semiconductor layer. One of a pair of source/drain regions of the second IGFET is electrically connected to one of a pair of source/drain regions of the first IGFET by a first interconnection diffusion region. A third IGFET of the first conductivity type is formed in the second area of the semiconductor layer.

Abstract: The present invention relates to a capacitor and a method of fabricating the same including a semiconductor substrate, an impurity region in the semiconductor substrate, a first insulating layer on the semiconductor substrate, the first insulating layer having a first contact hole to expose the impurity region, a first conductive layer in the contact hole, a second conductive layer on the first insulating layer, a second insulating layer on the first insulating layer including the second conductive layer, the second insulating layer contacting the first portion of the second conductive layer, a lower electrode on the second insulating layer, the lower electrode being not directly contacting the first conductive layer, a dielectric layer on the lower electrode including the second insulating layer, and an upper electrode on the dielectric layer.

Abstract: A semiconductor device which has an interlayer insulating film comprised of molecules with silicon-oxygen bonds and silicon-fluorine bonds and contains a rare gas in concentration higher than 10.sup.11 atoms per cm.sup.2. The interlayer insulating film is preferably a fluorine-containing silicon oxide film which contains a rare gas. In a manufacturing process, an interlayer insulating is formed by a chemical vapor deposition from a material gas including a silicon-containing gas, a fluorine compound gas, a rare gas, and oxygen. The silicon-containing gas is preferably SiH.sub.4 gas, and the fluorine compound gas is preferably SiF4 gas. The flow rate of the rare gas is greater than three times the total flow rate of the SiH.sub.4 gas and SiF.sub.4 gas. The rare gas is at least one type of gas selected from neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

Abstract: A semiconductor dynamic random access memory device includes plural memory cell arrays arranged in two columns, and the memory cell arrays of one column has memory cell sub-arrays and peripheral circuits such as sense amplifiers and sub-word line drivers arranged around the memory cell sub-arrays; the memory cells of the sub-arrays are arranged in a first pattern, and the peripheral circuits of adjacent sub-arrays are arranged in symmetry with respect to a line of symmetry perpendicular to the direction of the columns so as to increase a margin of alignment without sacrifice of simplicity of design work.

Abstract: A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1<A2, A3<A2 and A1<83.degree..

Abstract: A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate under a source diffusion layer is lower than the impurity concentration on a source side of a p-type impurity layer. Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: Improved conductive pads and conductive lines for use on integrated circuit chips include one or more conductive layers having a wider width than convention conductive lines for improved current and power carrying capacity. A layer of insulating and shock resistant is included over said layers of wider width, and additional pads can be formed on said layer of insulating and shock resistant material. Additional improved conductive pads are formed on the integrated circuit chip over a region containing a conductive line. The improved pads and conductive lines provide high power and current carrying capacity, and simultaneously allow for high pad density on an integrated circuit chip. Said pads and conductive lines can include a layer of metal which is electrically insulated using upper and lower layers of insulating material, with this layer of metal providing shock resistance particularly to such lower layer of insulating material.

Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

Abstract: There is provided an insulating gate type semiconductor device including (a) a semiconductor region defining a cell region and a field region, the cell region including a drain region, a base region, and a source region, a first recess being formed throughout the source region and reaching an intermediate depth of the base region, (b) a gate insulating film partially covering an exposed surface of the source region therewith, entirely covering an exposed surface of the base region, and partially covering an exposed surface of the drain region therewith, (c) a gate electrode formed on the gate insulating film, (d) a field insulating film formed on the semiconductor region in the field region, (e) a first gate wiring layer formed on the field insulating film in electrical connection with the gate electrode, the first gate wiring layer being formed with a second recess, (f) a source electrode in electrical isolation from the gate electrode, but in electrical connection with both an inner surface of the first rec

Abstract: The present invention relates to the fabrication of a boron carbide/boron diode on an aluminum substrate, and a boron carbide/boron junction field effect transistor. Our results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B.sub.5 C) acts as a p-type material. Both boron and boron carbide (B.sub.5 C) thin films were fabricated from single source borane cage molecules using plasma enhanced chemical vapor deposition (PECVD). Epitaxial growth does not appear to be a requirement. We have doped boron carbide grown by plasma enhanced chemical vapor deposition. The source gas closo-1,2-dicarbadecaborane (orthocarborane) was used to grow the boron carbide while nickelocene (Ni(C.sub.5 H.sub.5)2) was used to introduce nickel into the growing film. The doping of nickel transformed a B.sub.5 C material p-type relative to lightly doped n-type silicon to an n-type material.

Abstract: A coverage can be improved when an upper layer is formed on an upper wiring patterned on an interlayer insulation film. A sidewall made of an insulating material is bonded to a side face of the upper wiring patterned on the interlayer insulation film. Consequently, a height difference between the upper wiring and the interlayer insulation film has a small gradient. By flattening a laminated face of the upper layers including surfaces of the upper wiring and the sidewall, a further upper layer to be formed can have a coverage improved.

Abstract: A semiconductor device includes a high-power output transistor chip in which transistor cells are connected in parallel, each transistor cell including stripe-shaped gate electrodes connected to a gate bus, stripe-shaped drain electrodes connected to a drain pad, and stripe-shaped source electrodes connected to a source pad, wherein the drain electrodes and the source electrodes are alternatingly arranged and pairs of source and drain electrodes face each other across one of the gate electrodes; and a resistor including a portion of the gate bus between adjacent transistor cells, for preventing oscillation between the adjacent transistor cells. Since the resistor serves as a loss component, oscillation due to an imbalance in characteristics between adjacent transistor cells is cancelled so that the synthesis efficiency of the transistor cells is improved.

Abstract: Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads.

Abstract: A semiconductor multichip module includes a plurality of semiconductor chips, a static plate having a plurality of insertion holes for receiving the plurality of chips, a shield cap attached onto the lower surface of the static plate for preventing the chips from deviating downward through the insertion holes, an external terminal unit formed over the chips for externally transmitting electrical signals of the chips, and a plurality of clip-type clamp springs clamping the shield cap and the external terminal unit for preventing the chips from externally deviating. The multichip module improves productivity by decreasing production hours and enables effective chips to be easily replaced with normal chips by disassembling and reassembling the clamp springs.

Abstract: An LED chip 41 is mounted in a horizontal state in such a manner that a PN junction surface 42 is in perpendicular to a unit substrate 45. A side surface of a crystal surface of the LED chip 41 is recessed in such a manner as to have a distance with respect to a surface of the unit substrate 45, or is wholly covered by an electrically insulating film 52 formed of an ultraviolet curable type resin, so that even when the LED chip is in contact with wiring patterns 46, 47 of the unit substrate 45, an electric trouble such as an electrical short is not generated. An electrical connection to the LED chip 41 is performed by connecting thick film electrodes 53, 54 provided on both sides in a perpendicular direction to a PN junction surface, and the wiring patterns 46, 47 on the unit substrate 45 to each other through electrically conductive pastes 56, 57.

Abstract: The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 .ANG.. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700.degree. C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty.

Abstract: A method of inhibiting electrostatic discharge damage to an array of semiconductor switches (21) formed on a common substrate and arranged in rows and columns comprises the steps of: during formation of gate lines (24) that interconnect one of the rows and columns of the array, connecting one end of each gate line directly to a shorting ring (52) and another end of each gate line to a shorting ring (56) via a protection element (54); during formation of the source lines (26) that interconnect the other of the rows or columns of the array, connecting one end of each source line directly to a shorting ring (56) and connecting another end of each source line to a shorting ring (56) via a protection element (58); and electrically coupling the shorting rings (52, 56). A semiconductor switch array (21) incorporating electrostatic discharge protection (50) is also provided.